This commit is contained in:
Tom Verbeure 2019-03-24 23:56:23 +00:00
commit 3d5e941aef
3 changed files with 18 additions and 4 deletions

1
.gitignore vendored
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@ -1,6 +1,7 @@
*.class
*.log
*.bak
.*.swp
# sbt specific
.cache/

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@ -63,6 +63,12 @@ object DBusSimpleBus{
useBTE = true,
useCTI = true
)
def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
addressWidth = 32,
dataWidth = 32
)
}
case class DBusSimpleBus() extends Bundle with IMasterSlave{
@ -178,7 +184,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
}
def toPipelinedMemoryBus() : PipelinedMemoryBus = {
val bus = PipelinedMemoryBus(32,32)
val pipelinedMemoryBusConfig = DBusSimpleBus.getPipelinedMemoryBusConfig()
val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
bus.cmd.valid := cmd.valid
bus.cmd.write := cmd.wr
bus.cmd.address := cmd.address.resized

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@ -59,6 +59,11 @@ object IBusSimpleBus{
useBTE = true,
useCTI = true
)
def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
addressWidth = 32,
dataWidth = 32
)
}
@ -136,7 +141,8 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
}
def toPipelinedMemoryBus(): PipelinedMemoryBus = {
val bus = PipelinedMemoryBus(32,32)
val pipelinedMemoryBusConfig = IBusSimpleBus.getPipelinedMemoryBusConfig()
val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
bus.cmd.arbitrationFrom(cmd)
bus.cmd.address := cmd.pc.resized
bus.cmd.write := False