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DebugPlugin doesn't require memory/writeback stage anymore

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This commit is contained in:
Dolu1990 2018-12-01 18:24:33 +01:00
parent 58d7a4784d
commit 3d71045159
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/vexriscv/plugin/DebugPlugin.scala
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@ -141,7 +141,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
val haltIt = RegInit(False)
val stepIt = RegInit(False)
val isPipActive = RegNext(List(decode,execute, memory, writeBack).map(_.arbitration.isValid).orR)
val isPipActive = RegNext(stages.map(_.arbitration.isValid).orR)
val isPipBusy = isPipActive || RegNext(isPipActive)
val haltedByBreak = RegInit(False)
@ -152,8 +152,8 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
hardwareBreakpoints.foreach(_.valid init(False))
val busReadDataReg = Reg(Bits(32 bit))
when(writeBack.arbitration.isValid) {
busReadDataReg := writeBack.output(REGFILE_WRITE_DATA)
when(stages.last.arbitration.isValid) {
busReadDataReg := stages.last.output(REGFILE_WRITE_DATA)
}
io.bus.cmd.ready := True
io.bus.rsp.data := busReadDataReg
@ -199,7 +199,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
when(execute.arbitration.isValid && execute.input(DO_EBREAK)){
execute.arbitration.haltByOther := True
busReadDataReg := execute.input(PC).asBits
when(List(memory, writeBack).map(_.arbitration.isValid).orR === False){
when(stagesFromExecute.tail.map(_.arbitration.isValid).orR === False){
iBusFetcher.flushIt()
iBusFetcher.haltIt()
execute.arbitration.flushAll := True