Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

Update README.md

Browse source
This commit is contained in:
Dolu1990 2018-02-02 14:47:07 +01:00 committed by GitHub
parent f13dba847c
commit 3d97c1f2f2
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
README.md
View file

@ -99,7 +99,7 @@ There is a summary of the configuration which produce 1.40 DMIPS :
- memory load values are bypassed in the WB stage (late result) - memory load values are bypassed in the WB stage (late result)
- 33 cycle division with bypassing in the M stage (late result) - 33 cycle division with bypassing in the M stage (late result)
- single cycle multiplication with bypassing in the WB stage (late result) - single cycle multiplication with bypassing in the WB stage (late result)
- dynamic branch prediction done in the D stage with an direct mapped 2 bit branch history cache - dynamic branch prediction done in the F stage with an direct mapped target buffer cache (no penalities on corrects predictions)
## Dependencies ## Dependencies