Got multiway I$ D$ running linux fine.
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@ -40,13 +40,13 @@ cd VexRiscv
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Run regressions =>
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Run regressions =>
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sbt "runMain vexriscv.demo.LinuxGen -r"
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sbt "runMain vexriscv.demo.LinuxGen -r"
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cd src/test/cpp/regression
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cd src/test/cpp/regression
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make run IBUS=CACHED DBUS=SIMPLE DEBUG_PLUGIN=no DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=no DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no
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Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
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Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
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sbt "runMain vexriscv.demo.LinuxGen"
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sbt "runMain vexriscv.demo.LinuxGen"
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cd src/test/cpp/regression
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cd src/test/cpp/regression
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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make run IBUS=CACHED DBUS=SIMPLE DEBUG_PLUGIN=no SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=no SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
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Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
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Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
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@ -118,9 +118,9 @@ object LinuxGen {
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prediction = NONE,
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prediction = NONE,
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injectorStage = true,
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injectorStage = true,
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config = InstructionCacheConfig(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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cacheSize = 4096*2,
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bytePerLine = 32,
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bytePerLine = 32,
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wayCount = 1,
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wayCount = 2,
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addressWidth = 32,
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addressWidth = 32,
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cpuDataWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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memDataWidth = 32,
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@ -147,9 +147,9 @@ object LinuxGen {
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// ),
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// ),
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new DBusCachedPlugin(
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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config = new DataCacheConfig(
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cacheSize = 4096,
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cacheSize = 4096*2,
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bytePerLine = 32,
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bytePerLine = 32,
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wayCount = 1,
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wayCount = 2,
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addressWidth = 32,
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addressWidth = 32,
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cpuDataWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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memDataWidth = 32,
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@ -22,6 +22,10 @@ class DBusCachedPlugin(config : DataCacheConfig,
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memoryTranslatorPortConfig : Any = null,
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memoryTranslatorPortConfig : Any = null,
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csrInfo : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService {
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csrInfo : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService {
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import config._
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import config._
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assert(isPow2(cacheSize))
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assert(!(memoryTranslatorPortConfig != null && config.cacheSize/config.wayCount > 4096), "When the D$ is used with MMU, each way can't be bigger than a page (4096 bytes)")
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var dBus : DataCacheMemBus = null
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var dBus : DataCacheMemBus = null
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var mmuBus : MemoryTranslatorBus = null
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var mmuBus : MemoryTranslatorBus = null
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var exceptionBus : Flow[ExceptionCause] = null
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var exceptionBus : Flow[ExceptionCause] = null
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@ -47,6 +47,10 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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injectorStage = (!config.twoCycleCache && !withoutInjectorStage) || injectorStage){
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injectorStage = (!config.twoCycleCache && !withoutInjectorStage) || injectorStage){
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import config._
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import config._
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assert(isPow2(cacheSize))
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assert(!(memoryTranslatorPortConfig != null && config.cacheSize/config.wayCount > 4096), "When the I$ is used with MMU, each way can't be bigger than a page (4096 bytes)")
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assert(!(withoutInjectorStage && injectorStage))
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assert(!(withoutInjectorStage && injectorStage))
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var iBus : InstructionCacheMemBus = null
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var iBus : InstructionCacheMemBus = null
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