d$ / i$ toWishbone bridges can now be bigger than 32 bits
https://github.com/m-labs/VexRiscv-verilog/pull/12
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@ -77,9 +77,9 @@ case class DataCacheConfig(cacheSize : Int,
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)
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def getWishboneConfig() = WishboneConfig(
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addressWidth = 30,
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dataWidth = 32,
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selWidth = 4,
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addressWidth = 32-log2Up(memDataWidth/8),
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dataWidth = memDataWidth,
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selWidth = memDataBytes,
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useSTALL = false,
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useLOCK = false,
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useERR = true,
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@ -329,11 +329,12 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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val wishboneConfig = p.getWishboneConfig()
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val bus = Wishbone(wishboneConfig)
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val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
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val addressShift = log2Up(p.memDataWidth/8)
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val cmdBridge = Stream (DataCacheMemCmd(p))
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val isBurst = cmdBridge.isBurst
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cmdBridge.valid := cmd.valid
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cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ U"00") | (cmd.address(31 downto 2) @@ U"00"))
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cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits)))
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cmdBridge.wr := cmd.wr
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cmdBridge.mask := cmd.mask
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cmdBridge.data := cmd.data
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@ -353,7 +354,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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bus.ADR := cmdBridge.address >> 2
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bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
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bus.BTE := B"00"
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bus.SEL := cmdBridge.wr ? cmdBridge.mask | B"1111"
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bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)
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bus.WE := cmdBridge.wr
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bus.DAT_MOSI := cmdBridge.data
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@ -56,9 +56,9 @@ case class InstructionCacheConfig( cacheSize : Int,
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)
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def getWishboneConfig() = WishboneConfig(
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addressWidth = 30,
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dataWidth = 32,
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selWidth = 4,
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addressWidth = 32-log2Up(memDataWidth/8),
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dataWidth = memDataWidth,
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selWidth = memDataWidth/8,
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useSTALL = false,
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useLOCK = false,
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useERR = true,
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@ -228,10 +228,10 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
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val pending = counter =/= 0
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val lastCycle = counter === counter.maxValue
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bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter
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bus.ADR := (cmd.address >> widthOf(counter) + log2Up(p.memDataWidth/8)) @@ counter
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bus.CTI := lastCycle ? B"111" | B"010"
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bus.BTE := "00"
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bus.SEL := "1111"
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bus.SEL.setAll()
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bus.WE := False
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bus.DAT_MOSI.assignDontCare()
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bus.CYC := False
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