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VexRiscv
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d$ / i$ toWishbone bridges can now be bigger than 32 bits 

https://github.com/m-labs/VexRiscv-verilog/pull/12
This commit is contained in:
Dolu1990 2021-09-15 11:36:51 +02:00
parent efd3cd4737
commit 42bb1ab591
2 changed files with 11 additions and 10 deletions
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11
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -77,9 +77,9 @@ case class DataCacheConfig(cacheSize : Int,
) )
def getWishboneConfig() = WishboneConfig( def getWishboneConfig() = WishboneConfig(
addressWidth = 30, addressWidth = 32-log2Up(memDataWidth/8),
dataWidth = 32, dataWidth = memDataWidth,
selWidth = 4, selWidth = memDataBytes,
useSTALL = false, useSTALL = false,
useLOCK = false, useLOCK = false,
useERR = true, useERR = true,
@ -329,11 +329,12 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
val wishboneConfig = p.getWishboneConfig() val wishboneConfig = p.getWishboneConfig()
val bus = Wishbone(wishboneConfig) val bus = Wishbone(wishboneConfig)
val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0) val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
val addressShift = log2Up(p.memDataWidth/8)
val cmdBridge = Stream (DataCacheMemCmd(p)) val cmdBridge = Stream (DataCacheMemCmd(p))
val isBurst = cmdBridge.isBurst val isBurst = cmdBridge.isBurst
cmdBridge.valid := cmd.valid cmdBridge.valid := cmd.valid
cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ U"00") | (cmd.address(31 downto 2) @@ U"00")) cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits)))
cmdBridge.wr := cmd.wr cmdBridge.wr := cmd.wr
cmdBridge.mask := cmd.mask cmdBridge.mask := cmd.mask
cmdBridge.data := cmd.data cmdBridge.data := cmd.data
@ -353,7 +354,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
bus.ADR := cmdBridge.address >> 2 bus.ADR := cmdBridge.address >> 2
bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000") bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
bus.BTE := B"00" bus.BTE := B"00"
bus.SEL := cmdBridge.wr ? cmdBridge.mask | B"1111" bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)
bus.WE := cmdBridge.wr bus.WE := cmdBridge.wr
bus.DAT_MOSI := cmdBridge.data bus.DAT_MOSI := cmdBridge.data

10
src/main/scala/vexriscv/ip/InstructionCache.scala
View File

@ -56,9 +56,9 @@ case class InstructionCacheConfig( cacheSize : Int,
) )
def getWishboneConfig() = WishboneConfig( def getWishboneConfig() = WishboneConfig(
addressWidth = 30, addressWidth = 32-log2Up(memDataWidth/8),
dataWidth = 32, dataWidth = memDataWidth,
selWidth = 4, selWidth = memDataWidth/8,
useSTALL = false, useSTALL = false,
useLOCK = false, useLOCK = false,
useERR = true, useERR = true,
@ -228,10 +228,10 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
val pending = counter =/= 0 val pending = counter =/= 0
val lastCycle = counter === counter.maxValue val lastCycle = counter === counter.maxValue
bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter bus.ADR := (cmd.address >> widthOf(counter) + log2Up(p.memDataWidth/8)) @@ counter
bus.CTI := lastCycle ? B"111" | B"010" bus.CTI := lastCycle ? B"111" | B"010"
bus.BTE := "00" bus.BTE := "00"
bus.SEL := "1111" bus.SEL.setAll()
bus.WE := False bus.WE := False
bus.DAT_MOSI.assignDontCare() bus.DAT_MOSI.assignDontCare()
bus.CYC := False bus.CYC := False