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VexRiscvSmpClusterGen.dBusCmdMasterPipe option added

This commit is contained in:
Dolu1990 2020-12-01 13:51:03 +01:00
parent 832218dbec
commit 45ff78d068
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -159,7 +159,8 @@ object VexRiscvSmpClusterGen {
iCacheWays : Int = 2, iCacheWays : Int = 2,
dCacheWays : Int = 2, dCacheWays : Int = 2,
iBusRelax : Boolean = false, iBusRelax : Boolean = false,
earlyBranch : Boolean = false) = { earlyBranch : Boolean = false,
dBusCmdMasterPipe : Boolean = false) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
val config = VexRiscvConfig( val config = VexRiscvConfig(
@ -198,7 +199,7 @@ object VexRiscvSmpClusterGen {
) )
), ),
new DBusCachedPlugin( new DBusCachedPlugin(
dBusCmdMasterPipe = dBusWidth == 32, dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32,
dBusCmdSlavePipe = true, dBusCmdSlavePipe = true,
dBusRspSlavePipe = true, dBusRspSlavePipe = true,
relaxedMemoryTranslationRegister = true, relaxedMemoryTranslationRegister = true,