Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

IBusCachedPlugin default is two cycle cache with single cycle ram.

Browse source
This commit is contained in:
Dolu1990 2018-05-24 13:46:31 +02:00
parent 2f8ccc55b6
commit 485f35a1b5
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
View file

@ -29,7 +29,7 @@ object GenSmallAndProductiveICache extends App{
catchMemoryTranslationMiss = false, catchMemoryTranslationMiss = false,
asyncTagMemory = false, asyncTagMemory = false,
twoCycleRam = false, twoCycleRam = false,
twoCycleCache = false twoCycleCache = true
) )
), ),
new DBusSimplePlugin( new DBusSimplePlugin(

2
src/main/scala/vexriscv/ip/InstructionCache.scala
View file

@ -17,7 +17,7 @@ case class InstructionCacheConfig( cacheSize : Int,
catchAccessFault : Boolean, catchAccessFault : Boolean,
catchMemoryTranslationMiss : Boolean, catchMemoryTranslationMiss : Boolean,
asyncTagMemory : Boolean, asyncTagMemory : Boolean,
twoCycleCache : Boolean = false, twoCycleCache : Boolean = true,
twoCycleRam : Boolean = false, twoCycleRam : Boolean = false,
preResetFlush : Boolean = false){ preResetFlush : Boolean = false){