Briey Area down by 10% by spliting the memory system in two (System, Debug)
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37c338ec98
commit
4b5bf7d807
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@ -226,7 +226,7 @@ object TestsWorkspace {
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// val toplevel = new VexRiscv(configLight)
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// val toplevel = new VexRiscv(configLight)
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// val toplevel = new VexRiscv(configTest)
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// val toplevel = new VexRiscv(configTest)
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toplevel.rework {
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/*toplevel.rework {
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var iBus : AvalonMM = null
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var iBus : AvalonMM = null
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for (plugin <- toplevel.config.plugins) plugin match {
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for (plugin <- toplevel.config.plugins) plugin match {
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case plugin: IBusSimplePlugin => {
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case plugin: IBusSimplePlugin => {
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@ -274,7 +274,7 @@ object TestsWorkspace {
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}
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}
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case _ =>
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case _ =>
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}
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}
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}
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}*/
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// toplevel.writeBack.input(config.PC).addAttribute(Verilator.public)
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// toplevel.writeBack.input(config.PC).addAttribute(Verilator.public)
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// toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
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// toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
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@ -15,7 +15,7 @@ import spinal.lib.graphic.vga.{Vga, Axi4VgaCtrlGenerics, Axi4VgaCtrl}
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import spinal.lib.io.TriStateArray
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import spinal.lib.io.TriStateArray
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import spinal.lib.memory.sdram._
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import spinal.lib.memory.sdram._
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import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
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import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, SystemDebuggerConfig}
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import spinal.lib.system.debugger.{SystemDebugger, JtagBridge, JtagAxi4SharedDebugger, SystemDebuggerConfig}
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case class BrieyConfig(axiFrequency : HertzNumber,
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case class BrieyConfig(axiFrequency : HertzNumber,
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@ -132,12 +132,6 @@ class Briey(config: BrieyConfig) extends Component{
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CAS = 3
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CAS = 3
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)
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)
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val jtagCtrl = JtagAxi4SharedDebugger(SystemDebuggerConfig(
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memAddressWidth = 32,
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memDataWidth = 32,
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remoteCmdWidth = 1
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))
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val apbBridge = Axi4SharedToApb3Bridge(
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val apbBridge = Axi4SharedToApb3Bridge(
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addressWidth = 20,
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addressWidth = 20,
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@ -208,10 +202,10 @@ class Briey(config: BrieyConfig) extends Component{
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// portTlbSize = 4
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// portTlbSize = 4
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// )
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// )
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),
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),
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// new DBusSimplePlugin(
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAddressMisaligned = true,
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// catchAccessFault = true
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// catchAccessFault = true
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// ),
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// ),
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new DBusCachedPlugin(
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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config = new DataCacheConfig(
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cacheSize = 4096,
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cacheSize = 4096,
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@ -292,7 +286,7 @@ class Briey(config: BrieyConfig) extends Component{
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val cpu = new VexRiscv(configLight)
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val cpu = new VexRiscv(configLight)
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var iBus : Axi4ReadOnly = null
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var iBus : Axi4ReadOnly = null
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var dBus : Axi4Shared = null
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var dBus : Axi4Shared = null
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var debugBus : Apb3 = null
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var debugBus : DebugExtensionBus = null
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for(plugin <- configLight.plugins) plugin match{
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for(plugin <- configLight.plugins) plugin match{
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case plugin : IBusSimplePlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : IBusSimplePlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : IBusCachedPlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : IBusCachedPlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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@ -304,7 +298,7 @@ class Briey(config: BrieyConfig) extends Component{
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}
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}
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case plugin : DebugPlugin => {
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case plugin : DebugPlugin => {
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resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
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resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
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debugBus = plugin.io.bus.fromApb3()
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debugBus = plugin.io.bus
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}
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}
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case _ =>
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case _ =>
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}
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}
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@ -322,7 +316,6 @@ class Briey(config: BrieyConfig) extends Component{
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axiCrossbar.addConnections(
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axiCrossbar.addConnections(
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core.iBus -> List(ram.io.axi, sdramCtrl.io.axi),
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core.iBus -> List(ram.io.axi, sdramCtrl.io.axi),
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core.dBus -> List(ram.io.axi, sdramCtrl.io.axi, apbBridge.io.axi),
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core.dBus -> List(ram.io.axi, sdramCtrl.io.axi, apbBridge.io.axi),
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jtagCtrl.io.axi -> List(ram.io.axi, sdramCtrl.io.axi, apbBridge.io.axi),
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vgaCtrl.io.axi -> List( sdramCtrl.io.axi)
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vgaCtrl.io.axi -> List( sdramCtrl.io.axi)
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)
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)
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@ -370,16 +363,32 @@ class Briey(config: BrieyConfig) extends Component{
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gpioBCtrl.io.apb -> (0x01000, 4 kB),
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gpioBCtrl.io.apb -> (0x01000, 4 kB),
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uartCtrl.io.apb -> (0x10000, 4 kB),
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uartCtrl.io.apb -> (0x10000, 4 kB),
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timerCtrl.io.apb -> (0x20000, 4 kB),
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timerCtrl.io.apb -> (0x20000, 4 kB),
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vgaCtrl.io.apb -> (0x30000, 4 kB),
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vgaCtrl.io.apb -> (0x30000, 4 kB)
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core.debugBus -> (0xF0000, 4 kB)
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)
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)
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)
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)
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//Add JTAG
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val jtagConfig = SystemDebuggerConfig(
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memAddressWidth = 32,
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memDataWidth = 32,
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remoteCmdWidth = 1
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)
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val jtagBridge = new JtagBridge(jtagConfig)
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val debugger = new SystemDebugger(jtagConfig)
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debugger.io.remote <> jtagBridge.io.remote
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debugger.io.mem.cmd.valid <> core.debugBus.cmd.valid
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debugger.io.mem.cmd.ready <> core.debugBus.cmd.ready
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debugger.io.mem.cmd.wr <> core.debugBus.cmd.wr
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debugger.io.mem.cmd.address.resized <> core.debugBus.cmd.address
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debugger.io.mem.cmd.data <> core.debugBus.cmd.data
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debugger.io.mem.rsp.valid <> RegNext(core.debugBus.cmd.fire).init(False)
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debugger.io.mem.rsp.payload <> core.debugBus.rsp.data
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}
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}
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io.gpioA <> axi.gpioACtrl.io.gpio
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io.gpioA <> axi.gpioACtrl.io.gpio
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io.gpioB <> axi.gpioBCtrl.io.gpio
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io.gpioB <> axi.gpioBCtrl.io.gpio
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io.timerExternal <> axi.timerCtrl.io.external
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io.timerExternal <> axi.timerCtrl.io.external
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io.jtag <> axi.jtagCtrl.io.jtag
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io.jtag <> axi.jtagBridge.io.jtag
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io.uart <> axi.uartCtrl.io.uart
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io.uart <> axi.uartCtrl.io.uart
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io.sdram <> axi.sdramCtrl.io.sdram
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io.sdram <> axi.sdramCtrl.io.sdram
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io.vga <> axi.vgaCtrl.io.vga
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io.vga <> axi.vgaCtrl.io.vga
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@ -339,6 +339,10 @@ public:
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top->timerInterrupt = 0;
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top->timerInterrupt = 0;
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top->externalInterrupt = 1;
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top->externalInterrupt = 1;
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#endif
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#endif
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#ifdef DEBUG_PLUGIN_EXTERNAL
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top->timerInterrupt = 0;
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top->externalInterrupt = 0;
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#endif
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dump(0);
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dump(0);
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top->reset = 0;
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top->reset = 0;
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for(SimElement* simElement : simElements) simElement->postReset();
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for(SimElement* simElement : simElements) simElement->postReset();
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@ -379,6 +383,7 @@ public:
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top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0;
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top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0;
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//if(mTime == mTimeCmp) printf("SIM timer tick\n");
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//if(mTime == mTimeCmp) printf("SIM timer tick\n");
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#endif
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#endif
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currentTime = i;
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currentTime = i;
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@ -906,6 +911,10 @@ public:
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DebugPlugin(Workspace* ws){
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DebugPlugin(Workspace* ws){
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this->ws = ws;
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this->ws = ws;
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this->top = ws->top;
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this->top = ws->top;
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#ifdef DEBUG_PLUGIN_EXTERNAL
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ws->mTimeCmp = ~0;
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#endif
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top->debugReset = 0;
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top->debugReset = 0;
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@ -1003,13 +1012,13 @@ public:
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if((address & ~ 0x4) == 0xF00F0000){
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if((address & ~ 0x4) == 0xF00F0000){
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assert(size == 2);
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assert(size == 2);
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timeSpacer = 50;
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timeSpacer = 100;
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taskValid = true;
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taskValid = true;
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task.wr = wr;
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task.wr = wr;
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task.address = address;
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task.address = address;
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task.data = data;
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task.data = data;
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} else {
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}/* else {
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bool dummy;
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bool dummy;
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//printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data);
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//printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data);
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ws->dBusAccess(address,wr,size,0xFFFFFFFF, &data, &dummy);
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ws->dBusAccess(address,wr,size,0xFFFFFFFF, &data, &dummy);
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@ -1017,7 +1026,7 @@ public:
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//cout << hex << setw(8) << address << " -> " << hex << setw(8) << data << endl;
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//cout << hex << setw(8) << address << " -> " << hex << setw(8) << data << endl;
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if(-1 == send(clientHandle,&data,4,0)) connectionReset();
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if(-1 == send(clientHandle,&data,4,0)) connectionReset();
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}
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}
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}
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}*/
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}
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}
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} else {
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} else {
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int error = 0;
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int error = 0;
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@ -1575,8 +1584,8 @@ int main(int argc, char **argv, char **env) {
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w.loadHex("../../resources/hex/debugPluginExternal.hex");
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w.loadHex("../../resources/hex/debugPluginExternal.hex");
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w.noInstructionReadCheck();
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w.noInstructionReadCheck();
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#if defined(TRACE) || defined(TRACE_ACCESS)
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#if defined(TRACE) || defined(TRACE_ACCESS)
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w.setCyclesPerSecond(5e3);
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//w.setCyclesPerSecond(5e3);
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printf("Speed reduced 5Khz\n");
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//printf("Speed reduced 5Khz\n");
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#endif
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#endif
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w.run(1e9);
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w.run(1e9);
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}
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}
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