Briey Area down by 10% by spliting the memory system in two (System, Debug)

src/main/scala/VexRiscv/TestsWorkspace.scala

@@ -226,7 +226,7 @@ object TestsWorkspace {
 //      val toplevel = new VexRiscv(configLight)
 //      val toplevel = new VexRiscv(configTest)
 
-      toplevel.rework {
+      /*toplevel.rework {
         var iBus : AvalonMM = null
         for (plugin <- toplevel.config.plugins) plugin match {
           case plugin: IBusSimplePlugin => {
@@ -274,7 +274,7 @@ object TestsWorkspace {
           }
           case _ =>
         }
-      }
+      }*/
 //      toplevel.writeBack.input(config.PC).addAttribute(Verilator.public)
 //      toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
 

src/main/scala/VexRiscv/demo/Briey.scala

@@ -15,13 +15,13 @@ import spinal.lib.graphic.vga.{Vga, Axi4VgaCtrlGenerics, Axi4VgaCtrl}
 import spinal.lib.io.TriStateArray
 import spinal.lib.memory.sdram._
 import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
-import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, SystemDebuggerConfig}
+import spinal.lib.system.debugger.{SystemDebugger, JtagBridge, JtagAxi4SharedDebugger, SystemDebuggerConfig}
 
 
 case class BrieyConfig(axiFrequency : HertzNumber,
-                        onChipRamSize : BigInt,
+                       onChipRamSize : BigInt,
-                        sdramLayout: SdramLayout,
+                       sdramLayout: SdramLayout,
-                        sdramTimings: SdramTimings)
+                       sdramTimings: SdramTimings)
 
 object BrieyConfig{
   def default = {
@@ -132,12 +132,6 @@ class Briey(config: BrieyConfig) extends Component{
       CAS          = 3
     )
 
-    val jtagCtrl = JtagAxi4SharedDebugger(SystemDebuggerConfig(
-      memAddressWidth = 32,
-      memDataWidth    = 32,
-      remoteCmdWidth  = 1
-    ))
-
 
     val apbBridge = Axi4SharedToApb3Bridge(
       addressWidth = 20,
@@ -208,10 +202,10 @@ class Briey(config: BrieyConfig) extends Component{
             //              portTlbSize = 4
             //            )
           ),
-//                    new DBusSimplePlugin(
+          //                    new DBusSimplePlugin(
-//                      catchAddressMisaligned = true,
+          //                      catchAddressMisaligned = true,
-//                      catchAccessFault = true
+          //                      catchAccessFault = true
-//                    ),
+          //                    ),
           new DBusCachedPlugin(
             config = new DataCacheConfig(
               cacheSize         = 4096,
@@ -292,7 +286,7 @@ class Briey(config: BrieyConfig) extends Component{
       val cpu = new VexRiscv(configLight)
       var iBus : Axi4ReadOnly = null
       var dBus : Axi4Shared = null
-      var debugBus : Apb3 = null
+      var debugBus : DebugExtensionBus = null
       for(plugin <- configLight.plugins) plugin match{
         case plugin : IBusSimplePlugin => iBus = plugin.iBus.toAxi4ReadOnly()
         case plugin : IBusCachedPlugin => iBus = plugin.iBus.toAxi4ReadOnly()
@@ -304,7 +298,7 @@ class Briey(config: BrieyConfig) extends Component{
         }
         case plugin : DebugPlugin      => {
           resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
-          debugBus = plugin.io.bus.fromApb3()
+          debugBus = plugin.io.bus
         }
         case _ =>
       }
@@ -322,7 +316,6 @@ class Briey(config: BrieyConfig) extends Component{
     axiCrossbar.addConnections(
       core.iBus       -> List(ram.io.axi, sdramCtrl.io.axi),
       core.dBus       -> List(ram.io.axi, sdramCtrl.io.axi, apbBridge.io.axi),
-      jtagCtrl.io.axi -> List(ram.io.axi, sdramCtrl.io.axi, apbBridge.io.axi),
       vgaCtrl.io.axi  -> List(            sdramCtrl.io.axi)
     )
 
@@ -370,16 +363,32 @@ class Briey(config: BrieyConfig) extends Component{
         gpioBCtrl.io.apb -> (0x01000, 4 kB),
         uartCtrl.io.apb  -> (0x10000, 4 kB),
         timerCtrl.io.apb -> (0x20000, 4 kB),
-        vgaCtrl.io.apb   -> (0x30000, 4 kB),
+        vgaCtrl.io.apb   -> (0x30000, 4 kB)
-        core.debugBus    -> (0xF0000, 4 kB)
       )
     )
+
+    //Add JTAG
+    val jtagConfig = SystemDebuggerConfig(
+      memAddressWidth = 32,
+      memDataWidth    = 32,
+      remoteCmdWidth  = 1
+    )
+    val jtagBridge = new JtagBridge(jtagConfig)
+    val debugger = new SystemDebugger(jtagConfig)
+    debugger.io.remote <> jtagBridge.io.remote
+    debugger.io.mem.cmd.valid           <> core.debugBus.cmd.valid
+    debugger.io.mem.cmd.ready           <> core.debugBus.cmd.ready
+    debugger.io.mem.cmd.wr              <> core.debugBus.cmd.wr
+    debugger.io.mem.cmd.address.resized <> core.debugBus.cmd.address
+    debugger.io.mem.cmd.data            <> core.debugBus.cmd.data
+    debugger.io.mem.rsp.valid           <> RegNext(core.debugBus.cmd.fire).init(False)
+    debugger.io.mem.rsp.payload         <> core.debugBus.rsp.data
   }
 
   io.gpioA          <> axi.gpioACtrl.io.gpio
   io.gpioB          <> axi.gpioBCtrl.io.gpio
   io.timerExternal  <> axi.timerCtrl.io.external
-  io.jtag           <> axi.jtagCtrl.io.jtag
+  io.jtag           <> axi.jtagBridge.io.jtag
   io.uart           <> axi.uartCtrl.io.uart
   io.sdram          <> axi.sdramCtrl.io.sdram
   io.vga            <> axi.vgaCtrl.io.vga

src/test/cpp/regression/main.cpp

@@ -339,6 +339,10 @@ public:
 		top->timerInterrupt = 0;
 		top->externalInterrupt = 1;
 		#endif
+		#ifdef DEBUG_PLUGIN_EXTERNAL
+		top->timerInterrupt = 0;
+		top->externalInterrupt = 0;
+		#endif
 		dump(0);
 		top->reset = 0;
 		for(SimElement* simElement : simElements) simElement->postReset();
@@ -379,6 +383,7 @@ public:
 				top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0;
 				//if(mTime == mTimeCmp) printf("SIM timer tick\n");
 				#endif
+
 				currentTime = i;
 
 
@@ -906,6 +911,10 @@ public:
 	DebugPlugin(Workspace* ws){
 		this->ws = ws;
 		this->top = ws->top;
+
+		#ifdef DEBUG_PLUGIN_EXTERNAL
+			ws->mTimeCmp = ~0;
+		#endif
 		top->debugReset = 0;
 
 
@@ -1003,13 +1012,13 @@ public:
 
 						if((address & ~ 0x4) == 0xF00F0000){
 							assert(size == 2);
-							timeSpacer = 50;
+							timeSpacer = 100;
 
 							taskValid = true;
 							task.wr = wr;
 							task.address = address;
 							task.data = data;
-						} else {
+						}/* else {
 							bool dummy;
 							//printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data);
 							ws->dBusAccess(address,wr,size,0xFFFFFFFF, &data, &dummy);
@@ -1017,7 +1026,7 @@ public:
 								//cout << hex << setw(8) << address << " -> " << hex << setw(8) << data << endl;
 								if(-1 == send(clientHandle,&data,4,0))  connectionReset();
 							}
-						}
+						}*/
 					}
 				} else {
 					int error = 0;
@@ -1575,8 +1584,8 @@ int main(int argc, char **argv, char **env) {
 				w.loadHex("../../resources/hex/debugPluginExternal.hex");
 				w.noInstructionReadCheck();
 				#if defined(TRACE) || defined(TRACE_ACCESS)
-					w.setCyclesPerSecond(5e3);
+					//w.setCyclesPerSecond(5e3);
-					printf("Speed reduced 5Khz\n");
+					//printf("Speed reduced 5Khz\n");
 				#endif
 				w.run(1e9);
 			}