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Merge pull request #366 from robindust-ce/master 

Add missing parameter jtagHeaderIgnoreWidth
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Dolu1990 2023-09-26 17:39:49 +02:00 committed by GitHub
parent 5ef1bc775f 960f8682ea
commit 4e051ed2a3
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2 changed files with 3 additions and 3 deletions
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2
doc/nativeJtag/README.md
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@ -49,7 +49,7 @@ as given could move with future changes to the file:
``` ```
[254] val jtagCtrl = JtagTapInstructionCtrl() [254] val jtagCtrl = JtagTapInstructionCtrl()
[255] val tap = jtagCtrl.fromXilinxBscane2(userId = 2) [255] val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
[256] jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK)) [256] jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0)
``` ```
Changing the above lines, removes the Murax SoC’s JTAG ports as pins of the FPGA and inserts the BSCANE2 Xilinx Changing the above lines, removes the Murax SoC’s JTAG ports as pins of the FPGA and inserts the BSCANE2 Xilinx
Debug IP to which the JTAG signals are now connected. Debug IP to which the JTAG signals are now connected.

2
src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
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@ -168,7 +168,7 @@ object VexRiscvAhbLite3{
// // On Artix FPGA jtag : // // On Artix FPGA jtag :
// val jtagCtrl = JtagTapInstructionCtrl() // val jtagCtrl = JtagTapInstructionCtrl()
// val tap = jtagCtrl.fromXilinxBscane2(userId = 1) // val tap = jtagCtrl.fromXilinxBscane2(userId = 1)
// jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK)) // jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0)
} }
case _ => case _ =>
} }