SrcPlugin add decodeAddSub option
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@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv}
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import spinal.core._
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import spinal.core._
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class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{
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class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{
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override def build(pipeline: VexRiscv): Unit = {
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline._
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import pipeline.config._
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import pipeline.config._
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@ -27,9 +27,10 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean =
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)
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)
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}
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}
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val addSubStage = if(decodeAddSub) decode else execute
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if(separatedAddSub) {
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if(separatedAddSub) {
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execute plug new Area {
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addSubStage plug new Area {
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import execute._
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import addSubStage._
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// ADD, SUB
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// ADD, SUB
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val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits.addAttribute("keep")
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val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits.addAttribute("keep")
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@ -45,8 +46,8 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean =
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insert(SRC_LESS) := less
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insert(SRC_LESS) := less
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}
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}
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}else{
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}else{
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execute plug new Area {
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addSubStage plug new Area {
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import execute._
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import addSubStage._
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// ADD, SUB
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// ADD, SUB
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val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1), S(0))).asBits
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val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1), S(0))).asBits
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