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SrcPlugin add decodeAddSub option

This commit is contained in:
Dolu1990 2018-10-24 01:28:37 +02:00
parent 372063582c
commit 4ed4af6a3e
1 changed files with 6 additions and 5 deletions
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11
src/main/scala/vexriscv/plugin/SrcPlugin.scala
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@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv}
import spinal.core._
class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{
class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{
override def build(pipeline: VexRiscv): Unit = {
import pipeline._
import pipeline.config._
@ -27,9 +27,10 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean =
)
}
val addSubStage = if(decodeAddSub) decode else execute
if(separatedAddSub) {
execute plug new Area {
import execute._
addSubStage plug new Area {
import addSubStage._
// ADD, SUB
val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits.addAttribute("keep")
@ -45,8 +46,8 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean =
insert(SRC_LESS) := less
}
}else{
execute plug new Area {
import execute._
addSubStage plug new Area {
import addSubStage._
// ADD, SUB
val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1), S(0))).asBits