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VexRiscv
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Complain about wrong earlyBranch settings.

This commit is contained in:
Tom Verbeure 2019-04-06 12:58:19 -07:00
parent 39a4aa5e26
commit 4fd36454d7
1 changed files with 4 additions and 1 deletions
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5
src/main/scala/vexriscv/plugin/BranchPlugin.scala
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@ -55,6 +55,7 @@ class BranchPlugin(earlyBranch : Boolean,
fenceiGenAsAJump : Boolean = false, fenceiGenAsAJump : Boolean = false,
fenceiGenAsANop : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ fenceiGenAsANop : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{
def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN) def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN)
lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory
@ -88,6 +89,8 @@ class BranchPlugin(earlyBranch : Boolean,
import pipeline.config._ import pipeline.config._
import IntAluPlugin._ import IntAluPlugin._
assert(earlyBranch || withMemoryStage, "earlyBranch must be true when memory stage is disabled!")
val bActions = List[(Stageable[_ <: BaseType],Any)]( val bActions = List[(Stageable[_ <: BaseType],Any)](
SRC1_CTRL -> Src1CtrlEnum.RS, SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS, SRC2_CTRL -> Src2CtrlEnum.RS,
@ -375,4 +378,4 @@ class BranchPlugin(earlyBranch : Boolean,
} }
} }
} }
} }