CSR Plugin now implement interruptions as specified in the spec
This commit is contained in:
Dolu1990
parent
3652ede130
commit
505bff6f45
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@ -282,8 +282,8 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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}
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var jumpInterface : Flow[UInt] = null
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var timerInterrupt, externalInterrupt : Bool = null
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var timerInterruptS, externalInterruptS : Bool = null
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var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null
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var externalInterruptS : Bool = null
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var privilege : UInt = null
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var selfException : Flow[ExceptionCause] = null
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var contextSwitching : Bool = null
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@ -376,8 +376,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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timerInterrupt = in Bool() setName("timerInterrupt")
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externalInterrupt = in Bool() setName("externalInterrupt")
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softwareInterrupt = in Bool() setName("softwareInterrupt")
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if(supervisorGen){
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timerInterruptS = in Bool() setName("timerInterruptS")
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// timerInterruptS = in Bool() setName("timerInterruptS")
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externalInterruptS = in Bool() setName("externalInterruptS")
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}
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contextSwitching = Bool().setName("contextSwitching")
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@ -444,9 +445,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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val MPP = RegInit(U"11")
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}
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val mip = new Area{
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val MEIP = RegNext(externalInterrupt) init(False)
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val MTIP = RegNext(timerInterrupt) init(False)
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val MSIP = RegInit(False)
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val MEIP = RegNext(externalInterrupt)
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val MTIP = RegNext(timerInterrupt)
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val MSIP = RegNext(softwareInterrupt)
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}
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val mie = new Area{
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val MEIE, MTIE, MSIE = RegInit(False)
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@ -503,8 +504,10 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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}
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val sip = new Area {
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val SEIP = RegNext(externalInterruptS) init (False)
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val STIP = RegNext(timerInterruptS) init (False)
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val SEIP_SOFT = RegInit(False)
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val SEIP_INPUT = RegNext(externalInterruptS)
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val SEIP_OR = SEIP_SOFT || SEIP_INPUT
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val STIP = RegInit(False)
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val SSIP = RegInit(False)
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}
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val sie = new Area {
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@ -528,8 +531,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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//Supervisor CSR
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for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) READ_WRITE(offset,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE)
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for(offset <- List(CSR.MIP, CSR.SIP)) {
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READ_ONLY(offset, 9 -> sip.SEIP, 5 -> sip.STIP)
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READ_WRITE(offset, 1 -> sip.SSIP)
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READ_WRITE(offset, 9 -> sip.SEIP_SOFT, 5 -> sip.STIP, 1 -> sip.SSIP)
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}
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for(offset <- List(CSR.MIE, CSR.SIE)) READ_WRITE(offset, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE)
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@ -566,7 +568,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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getInterruptPrivilege(1).sources ++= List(
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InterruptSource(sip.STIP && sie.STIE, 5),
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InterruptSource(sip.SSIP && sie.SSIE, 1),
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InterruptSource(sip.SEIP && sie.SEIE, 9)
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InterruptSource(sip.SEIP_OR && sie.SEIE, 9)
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)
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}
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@ -1,6 +1,5 @@
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RISCV_PATH?=/opt/riscv/
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CFLAGS += -march=rv32i -mabi=ilp32
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RISCV_NAME = riscv64-unknown-elf
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RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
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RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
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@ -8,6 +7,19 @@ RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/
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RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc
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LDSCRIPT=src/ld
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MABI=ilp32
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MARCH := rv32i
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ifeq ($(MULDIV),yes)
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MARCH := $(MARCH)m
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endif
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ifeq ($(COMPRESSED),yes)
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MARCH := $(MARCH)ac
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endif
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CFLAGS += -march=$(MARCH) -mabi=$(MABI)
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LDFLAGS += -march=$(MARCH) -mabi=$(MABI)
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SRCS = $(wildcard src/*.c) \
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$(wildcard src/*.cpp) \
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@ -0,0 +1,4 @@
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*.map
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*.v
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*.elf
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*.o
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@ -0,0 +1,138 @@
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build/machineCsr.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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80000000 <trap_entry-0x20>:
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80000000: 0940006f j 80000094 <_start>
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80000004: 00000013 nop
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80000008: 00000013 nop
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8000000c: 00000013 nop
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80000010: 00000013 nop
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80000014: 00000013 nop
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80000018: 00000013 nop
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8000001c: 00000013 nop
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80000020 <trap_entry>:
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80000020: 34202e73 csrr t3,mcause
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80000024: 000e1e63 bnez t3,80000040 <notICmdAlignementException>
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80000028: ffc00f13 li t5,-4
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8000002c: 34102ef3 csrr t4,mepc
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80000030: 01eefeb3 and t4,t4,t5
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80000034: 004e8e93 addi t4,t4,4
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80000038: 341e9073 csrw mepc,t4
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8000003c: 01c0006f j 80000058 <mepcFixed>
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80000040 <notICmdAlignementException>:
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80000040: 80000eb7 lui t4,0x80000
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80000044: 01de7f33 and t5,t3,t4
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80000048: 000f1863 bnez t5,80000058 <mepcFixed>
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8000004c: 34102ef3 csrr t4,mepc
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80000050: 004e8e93 addi t4,t4,4 # 80000004 <_start+0xffffff70>
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80000054: 341e9073 csrw mepc,t4
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80000058 <mepcFixed>:
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80000058: 80000eb7 lui t4,0x80000
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8000005c: 003e8e93 addi t4,t4,3 # 80000003 <_start+0xffffff6f>
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80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt>
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80000064: f0013c37 lui s8,0xf0013
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80000068: 00000c93 li s9,0
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8000006c: 019c2023 sw s9,0(s8) # f0013000 <_start+0x70012f6c>
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80000070 <noSoftwareInterrupt>:
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80000070: 80000eb7 lui t4,0x80000
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80000074: 007e8e93 addi t4,t4,7 # 80000007 <_start+0xffffff73>
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80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt>
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8000007c: 30405073 csrwi mie,0
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80000080 <noTimerInterrupt>:
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80000080: 80000eb7 lui t4,0x80000
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80000084: 00be8e93 addi t4,t4,11 # 8000000b <_start+0xffffff77>
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80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt>
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8000008c: 30405073 csrwi mie,0
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80000090 <noExernalInterrupt>:
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80000090: 30200073 mret
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80000094 <_start>:
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80000094: 00100e13 li t3,1
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80000098: 00000073 ecall
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8000009c: 00200e13 li t3,2
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800000a0: 00800293 li t0,8
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800000a4: 3002a073 csrs mstatus,t0
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800000a8: 00800293 li t0,8
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800000ac: 30429073 csrw mie,t0
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800000b0: f0013c37 lui s8,0xf0013
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800000b4: 00100c93 li s9,1
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800000b8: 019c2023 sw s9,0(s8) # f0013000 <_start+0x70012f6c>
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800000bc: 00000013 nop
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800000c0: 00000013 nop
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800000c4: 00000013 nop
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800000c8: 00000013 nop
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800000cc: 00000013 nop
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800000d0: 00000013 nop
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800000d4: 00000013 nop
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800000d8: 00000013 nop
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800000dc: 00000013 nop
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800000e0: 00000013 nop
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800000e4: 00000013 nop
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800000e8: 00000013 nop
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800000ec: 00300e13 li t3,3
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800000f0: 08000293 li t0,128
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800000f4: 30429073 csrw mie,t0
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800000f8: 00000013 nop
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800000fc: 00000013 nop
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80000100: 00000013 nop
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80000104: 00000013 nop
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80000108: 00000013 nop
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8000010c: 00000013 nop
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80000110: 00000013 nop
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80000114: 00400e13 li t3,4
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80000118: 000012b7 lui t0,0x1
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8000011c: 80028293 addi t0,t0,-2048 # 800 <trap_entry-0x7ffff820>
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80000120: 30429073 csrw mie,t0
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80000124: 00000013 nop
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80000128: 00000013 nop
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8000012c: 00000013 nop
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80000130: 00000013 nop
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80000134: 00000013 nop
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80000138: 00000013 nop
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8000013c: 00000013 nop
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80000140: 00500e13 li t3,5
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80000144: f01001b7 lui gp,0xf0100
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80000148: f4018193 addi gp,gp,-192 # f00fff40 <_start+0x700ffeac>
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8000014c: 0001a203 lw tp,0(gp)
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80000150: 0041a283 lw t0,4(gp)
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80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21>
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80000158: 0041a423 sw tp,8(gp)
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8000015c: 0051a623 sw t0,12(gp)
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80000160: 00600e13 li t3,6
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80000164: 08000213 li tp,128
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80000168: 30421073 csrw mie,tp
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8000016c: 00700e13 li t3,7
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80000170: 10500073 wfi
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80000174: 00800e13 li t3,8
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80000178: 00100193 li gp,1
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8000017c: 0041a023 sw tp,0(gp)
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80000180: 00900e13 li t3,9
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80000184: 00419023 sh tp,0(gp)
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80000188: 00a00e13 li t3,10
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8000018c: 0001a203 lw tp,0(gp)
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80000190: 00b00e13 li t3,11
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80000194: 00019203 lh tp,0(gp)
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80000198: 00c00e13 li t3,12
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8000019c: 00d00e13 li t3,13
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800001a0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
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800001a4: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
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800001a8: 00e00e13 li t3,14
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800001ac: 20200073 hret
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800001b0: 00f00e13 li t3,15
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800001b4: f01000b7 lui ra,0xf0100
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800001b8: f6008093 addi ra,ra,-160 # f00fff60 <_start+0x700ffecc>
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800001bc: 0000a103 lw sp,0(ra)
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800001c0: 01000e13 li t3,16
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800001c4: 0020a023 sw sp,0(ra)
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800001c8: 01100e13 li t3,17
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800001cc: 00008067 ret
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...
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@ -0,0 +1,33 @@
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:0200000480007A
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:100000006F004009130000001300000013000000FF
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:100010001300000013000000130000001300000094
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:10002000732E2034631E0E00130FC0FFF32E103406
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:10003000B3FEEE01938E4E0073901E346F00C0012C
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:10004000B70E0080337FDE0163180F00F32E1034EB
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:10005000938E4E0073901E34B70E0080938E3E0038
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:100060006398CE01373C01F0930C000023209C01E3
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:10007000B70E0080938E7E006394CE0173504030A3
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:10008000B70E0080938EBE006394CE017350403053
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:1000900073002030130E100073000000130E2000B8
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:1000A0009302800073A0023093028000739042306C
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:1000B000373C01F0930C100023209C01130000003A
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:1000C00013000000130000001300000013000000E4
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:1000D00013000000130000001300000013000000D4
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:1000E000130000001300000013000000130E300086
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:1000F00093020008739042301300000013000000C8
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:1001000013000000130000001300000013000000A3
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:1001100013000000130E4000B7120000938202800B
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:100120007390423013000000130000001300000021
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:100130001300000013000000130000001300000073
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:10014000130E5000B70110F0938101F403A20100D7
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:1001500083A241001302F23F23A4410023A65100D1
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:10016000130E60001302000873104230130E70006B
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:1001700073005010130E80009301100023A0410063
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:10018000130E900023904100130EA00003A2010063
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:10019000130EB00003920100130EC000130ED00026
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:1001A0008320000083200000130EE0007300202055
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:1001B000130EF000B70010F0938000F603A10000CA
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:1001C000130E000123A02000130E10016780000011
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:1001D000000000000000000000000000000000001F
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:0400000580000094E3
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:00000001FF
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@ -0,0 +1,139 @@
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build/machineCsrCompressed.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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80000000 <trap_entry-0x20>:
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80000000: a071 j 8000008c <_start>
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80000002: 0001 nop
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80000004: 00000013 nop
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80000008: 00000013 nop
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8000000c: 00000013 nop
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80000010: 00000013 nop
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80000014: 00000013 nop
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80000018: 00000013 nop
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8000001c: 00000013 nop
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80000020 <trap_entry>:
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80000020: 34202e73 csrr t3,mcause
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80000024: 000e1c63 bnez t3,8000003c <notICmdAlignementException>
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80000028: ffc00f13 li t5,-4
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8000002c: 34102ef3 csrr t4,mepc
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80000030: 01eefeb3 and t4,t4,t5
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80000034: 0e91 addi t4,t4,4
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80000036: 341e9073 csrw mepc,t4
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8000003a: a821 j 80000052 <mepcFixed>
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8000003c <notICmdAlignementException>:
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8000003c: 80000eb7 lui t4,0x80000
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80000040: 01de7f33 and t5,t3,t4
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80000044: 000f1763 bnez t5,80000052 <mepcFixed>
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80000048: 34102ef3 csrr t4,mepc
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8000004c: 0e91 addi t4,t4,4
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8000004e: 341e9073 csrw mepc,t4
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80000052 <mepcFixed>:
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80000052: 80000eb7 lui t4,0x80000
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80000056: 003e8e93 addi t4,t4,3 # 80000003 <_start+0xffffff77>
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8000005a: 01ce9763 bne t4,t3,80000068 <noSoftwareInterrupt>
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8000005e: f0013c37 lui s8,0xf0013
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80000062: 4c81 li s9,0
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80000064: 019c2023 sw s9,0(s8) # f0013000 <_start+0x70012f74>
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80000068 <noSoftwareInterrupt>:
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80000068: 80000eb7 lui t4,0x80000
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8000006c: 007e8e93 addi t4,t4,7 # 80000007 <_start+0xffffff7b>
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80000070: 01ce9463 bne t4,t3,80000078 <noTimerInterrupt>
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80000074: 30405073 csrwi mie,0
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80000078 <noTimerInterrupt>:
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80000078: 80000eb7 lui t4,0x80000
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8000007c: 00be8e93 addi t4,t4,11 # 8000000b <_start+0xffffff7f>
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80000080: 01ce9463 bne t4,t3,80000088 <noExernalInterrupt>
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80000084: 30405073 csrwi mie,0
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80000088 <noExernalInterrupt>:
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80000088: 30200073 mret
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8000008c <_start>:
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8000008c: 4e05 li t3,1
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8000008e: 00000073 ecall
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80000092: 4e09 li t3,2
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80000094: 42a1 li t0,8
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80000096: 3002a073 csrs mstatus,t0
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8000009a: 42a1 li t0,8
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8000009c: 30429073 csrw mie,t0
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800000a0: f0013c37 lui s8,0xf0013
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800000a4: 4c85 li s9,1
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800000a6: 019c2023 sw s9,0(s8) # f0013000 <_start+0x70012f74>
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800000aa: 0001 nop
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800000ac: 0001 nop
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800000ae: 0001 nop
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800000b0: 0001 nop
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800000b2: 0001 nop
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800000b4: 0001 nop
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800000b6: 0001 nop
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800000b8: 0001 nop
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800000ba: 0001 nop
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800000bc: 0001 nop
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800000be: 0001 nop
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800000c0: 0001 nop
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800000c2: 4e0d li t3,3
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800000c4: 08000293 li t0,128
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800000c8: 30429073 csrw mie,t0
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800000cc: 0001 nop
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800000ce: 0001 nop
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800000d0: 0001 nop
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800000d2: 0001 nop
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800000d4: 0001 nop
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800000d6: 0001 nop
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800000d8: 0001 nop
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800000da: 4e11 li t3,4
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800000dc: 000012b7 lui t0,0x1
|
||||
800000e0: 80028293 addi t0,t0,-2048 # 800 <trap_entry-0x7ffff820>
|
||||
800000e4: 30429073 csrw mie,t0
|
||||
800000e8: 0001 nop
|
||||
800000ea: 0001 nop
|
||||
800000ec: 0001 nop
|
||||
800000ee: 0001 nop
|
||||
800000f0: 0001 nop
|
||||
800000f2: 0001 nop
|
||||
800000f4: 0001 nop
|
||||
800000f6: 4e15 li t3,5
|
||||
800000f8: f01001b7 lui gp,0xf0100
|
||||
800000fc: f4018193 addi gp,gp,-192 # f00fff40 <_start+0x700ffeb4>
|
||||
80000100: 0001a203 lw tp,0(gp)
|
||||
80000104: 0041a283 lw t0,4(gp)
|
||||
80000108: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21>
|
||||
8000010c: 0041a423 sw tp,8(gp)
|
||||
80000110: 0051a623 sw t0,12(gp)
|
||||
80000114: 4e19 li t3,6
|
||||
80000116: 08000213 li tp,128
|
||||
8000011a: 30421073 csrw mie,tp
|
||||
8000011e: 4e1d li t3,7
|
||||
80000120: 10500073 wfi
|
||||
80000124: 4e21 li t3,8
|
||||
80000126: 4185 li gp,1
|
||||
80000128: 0041a023 sw tp,0(gp)
|
||||
8000012c: 4e25 li t3,9
|
||||
8000012e: 00419023 sh tp,0(gp)
|
||||
80000132: 4e29 li t3,10
|
||||
80000134: 0001a203 lw tp,0(gp)
|
||||
80000138: 4e2d li t3,11
|
||||
8000013a: 00019203 lh tp,0(gp)
|
||||
8000013e: 4e31 li t3,12
|
||||
80000140: 4e35 li t3,13
|
||||
80000142: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
|
||||
80000146: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
|
||||
8000014a: 4e39 li t3,14
|
||||
8000014c: 20200073 hret
|
||||
80000150: 4e3d li t3,15
|
||||
80000152: f01000b7 lui ra,0xf0100
|
||||
80000156: f6008093 addi ra,ra,-160 # f00fff60 <_start+0x700ffed4>
|
||||
8000015a: 0000a103 lw sp,0(ra)
|
||||
8000015e: 4e41 li t3,16
|
||||
80000160: 0020a023 sw sp,0(ra)
|
||||
80000164: 4e45 li t3,17
|
||||
80000166: 8082 ret
|
||||
...
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
:0200000480007A
|
||||
:1000000071A00100130000001300000013000000A5
|
||||
:100010001300000013000000130000001300000094
|
||||
:10002000732E2034631C0E00130FC0FFF32E103408
|
||||
:10003000B3FEEE01910E73901E3421A8B70E00801E
|
||||
:10004000337FDE0163170F00F32E1034910E73908F
|
||||
:100050001E34B70E0080938E3E006397CE01373C6E
|
||||
:1000600001F0814C23209C01B70E0080938E7E000E
|
||||
:100070006394CE0173504030B70E0080938EBE0063
|
||||
:100080006394CE017350403073002030054E7300EE
|
||||
:100090000000094EA14273A00230A1427390423089
|
||||
:1000A000373C01F0854C23209C0101000100010038
|
||||
:1000B0000100010001000100010001000100010038
|
||||
:1000C00001000D4E930200087390423001000100C0
|
||||
:1000D00001000100010001000100114EB7120000F3
|
||||
:1000E0009382028073904230010001000100010000
|
||||
:1000F000010001000100154EB70110F0938101F4D9
|
||||
:1001000003A2010083A241001302F23F23A4410095
|
||||
:1001100023A65100194E13020008731042301D4EE1
|
||||
:1001200073005010214E854123A04100254E23909D
|
||||
:100130004100294E03A201002D4E03920100314ED1
|
||||
:10014000354E8320000083200000394E73002020AC
|
||||
:100150003D4EB70010F0938000F603A10000414E21
|
||||
:1001600023A02000454E8280000000000000000017
|
||||
:10017000000000000000000000000000000000007F
|
||||
:040000058000008CEB
|
||||
:00000001FF
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
ifeq ($(COMPRESSED),yes)
|
||||
PROJ_NAME=machineCsrCompressed
|
||||
else
|
||||
PROJ_NAME=machineCsr
|
||||
endif
|
||||
|
||||
|
||||
|
||||
|
||||
include ../common/asm.mk
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
j _start
|
||||
|
||||
#define writeSoftwareInterrupt(value) \
|
||||
li x24, 0xF0013000; \
|
||||
li x25, value; \
|
||||
sw x25, 0(x24); \
|
||||
|
||||
.align 5
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
csrr x28, mcause
|
||||
|
||||
bnez x28, notICmdAlignementException
|
||||
li x30, 0xFFFFFFFC
|
||||
csrr x29, mepc
|
||||
and x29,x29,x30
|
||||
addi x29, x29, 4
|
||||
csrw mepc, x29
|
||||
j mepcFixed
|
||||
|
||||
notICmdAlignementException:
|
||||
li x29, 0x80000000
|
||||
and x30, x28, x29
|
||||
bnez x30, mepcFixed
|
||||
csrr x29, mepc
|
||||
addi x29, x29, 4
|
||||
csrw mepc, x29
|
||||
mepcFixed:
|
||||
|
||||
|
||||
li x29, 0x80000003u
|
||||
bne x29, x28, noSoftwareInterrupt
|
||||
writeSoftwareInterrupt(0)
|
||||
|
||||
noSoftwareInterrupt:
|
||||
|
||||
li x29, 0x80000007u
|
||||
bne x29, x28, noTimerInterrupt
|
||||
csrw mie, 0
|
||||
noTimerInterrupt:
|
||||
|
||||
li x29, 0x8000000bu
|
||||
bne x29, x28, noExernalInterrupt
|
||||
csrw mie, 0
|
||||
noExernalInterrupt:
|
||||
|
||||
mret
|
||||
|
||||
|
||||
.text
|
||||
.globl _start
|
||||
_start:
|
||||
li x28, 1
|
||||
ecall
|
||||
|
||||
li x28, 2
|
||||
li t0, 0x008
|
||||
csrs mstatus,t0
|
||||
li t0, 0x008
|
||||
csrw mie,t0
|
||||
writeSoftwareInterrupt(1)
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
|
||||
li x28, 3
|
||||
li t0, 0x080
|
||||
csrw mie,t0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
li x28, 4
|
||||
li t0, 0x800
|
||||
csrw mie,t0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
li x28, 5
|
||||
li x3, 0xF00FFF40
|
||||
lw x4, 0(x3)
|
||||
lw x5, 4(x3)
|
||||
addi x4, x4, 1023
|
||||
sw x4, 8(x3)
|
||||
sw x5, 12(x3)
|
||||
li x28, 6
|
||||
li x4, 0x080
|
||||
csrw mie,x4
|
||||
li x28, 7
|
||||
wfi
|
||||
|
||||
|
||||
li x28, 8
|
||||
li x3, 1
|
||||
sw x4,0(x3)
|
||||
li x28, 9
|
||||
sh x4,0(x3)
|
||||
li x28, 10
|
||||
lw x4,0(x3)
|
||||
li x28, 11
|
||||
lh x4,0(x3)
|
||||
li x28, 12
|
||||
|
||||
|
||||
|
||||
li x28, 13
|
||||
lw x1,0(x0)
|
||||
#ifdef COMPRESSED
|
||||
unalignedPcA:
|
||||
j unalignedPcA+2
|
||||
#endif
|
||||
lw x1,0(x0)
|
||||
|
||||
li x28, 14
|
||||
hret
|
||||
li x28, 15
|
||||
|
||||
|
||||
li x1, 0xF00FFF60
|
||||
lw x2, 0(x1)
|
||||
li x28, 16
|
||||
sw x2, 0(x1)
|
||||
li x28, 17
|
||||
jr x1
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
MEMORY {
|
||||
onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.crt_section :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*crt.o(.text)
|
||||
} > onChipRam
|
||||
|
||||
}
|
||||
|
|
@ -1162,9 +1162,11 @@ public:
|
|||
#ifdef EXTERNAL_INTERRUPT
|
||||
case 0xF0011000u: top->externalInterrupt = *data & 1; break;
|
||||
#endif
|
||||
|
||||
#ifdef SUPERVISOR
|
||||
case 0xF0012000u: top->externalInterruptS = *data & 1; break;
|
||||
#endif
|
||||
#ifdef CSR
|
||||
case 0xF0013000u: top->softwareInterrupt = *data & 1; break;
|
||||
#endif
|
||||
case 0xF00FFF00u: {
|
||||
cout << mem[0xF00FFF00u];
|
||||
|
|
@ -1275,6 +1277,7 @@ public:
|
|||
#ifdef CSR
|
||||
top->timerInterrupt = 0;
|
||||
top->externalInterrupt = 1;
|
||||
top->softwareInterrupt = 0;
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
top->externalInterruptS = 0;
|
||||
|
|
@ -1364,8 +1367,11 @@ public:
|
|||
#ifdef EXTERNAL_INTERRUPT
|
||||
riscvRef.interrupts |= top->externalInterrupt << 11;
|
||||
#endif
|
||||
#ifdef CSR
|
||||
riscvRef.interrupts |= top->softwareInterrupt << 3;
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
riscvRef.interrupts |= top->timerInterruptS << 5;
|
||||
// riscvRef.interrupts |= top->timerInterruptS << 5;
|
||||
riscvRef.interrupts |= top->externalInterruptS << 9;
|
||||
#endif
|
||||
|
||||
|
|
@ -3114,11 +3120,11 @@ int main(int argc, char **argv, char **env) {
|
|||
#ifndef COMPRESSED
|
||||
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
|
||||
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };
|
||||
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);)
|
||||
redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);)
|
||||
#else
|
||||
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
|
||||
8,6,9,6,10,4,11,4, 12,13, 14,2, 15,5,16,17,1 };
|
||||
redo(REDO,TestX28("machineCsrCompressed",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);)
|
||||
redo(REDO,TestX28("../../cpp/raw/machineCsr/build/machineCsrCompressed",machineCsrRef, sizeof(machineCsrRef)/4).withRiscvRef()->noInstructionReadCheck()->run(10e4);)
|
||||
#endif
|
||||
#endif
|
||||
// #ifdef MMU
|
||||
|
|
|
|||
Loading…
Reference in New Issue