Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

readme add features

This commit is contained in:
Dolu1990 2017-07-16 19:06:05 +02:00
parent 59e09ce269
commit 5190ba28e0
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
README.md
View File

@ -16,14 +16,15 @@
This repository host an RISC-V implementation written in SpinalHDL. There is some specs : This repository host an RISC-V implementation written in SpinalHDL. There is some specs :
- RV32IM instruction set - RV32IM instruction set
- Interrupts and exception handling with the Machine mode from the riscv-privileged-v1.9.1 specification.
- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack) - Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
- 1.16 DMIPS/Mhz when all features are enabled extension - 1.16 DMIPS/Mhz when all features are enabled extension
- Optimized for FPGA - Optimized for FPGA
- Optional MUL/DIV/REM extension - Optional MUL/DIV extension
- Optional instruction and data caches - Optional instruction and data caches
- Optional MMU - Optional MMU
- Two implementation of shift instructions, Single cycle / shiftNumber cycle - Optional debug extension allowing GDB debugging via an openOCD JTAG connection
- Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec.
- Two implementation of shift instructions, Single cycle / shiftNumber cycles
- Each stage could have bypass or interlock hazard logic - Each stage could have bypass or interlock hazard logic
- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV - FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV