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SimpleBusInterconnect now adapte address width

This commit is contained in:
Dolu1990 2018-10-28 02:18:08 +02:00
parent 00bf84b7f8
commit 51de2b5820
2 changed files with 10 additions and 2 deletions
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2
src/main/scala/vexriscv/demo/MuraxUtiles.scala
View File

@ -52,7 +52,7 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
}
class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
case class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
val io = new Bundle{
val bus = slave(SimpleBus(simpleBusConfig))
}

10
src/main/scala/vexriscv/demo/SimpleBus.scala
View File

@ -271,7 +271,15 @@ case class SimpleBusInterconnect(){
}
for(connection <- connections){
connection.connector(connectionsInput(connection), connectionsOutput(connection))
val m = connectionsInput(connection)
val s = connectionsOutput(connection)
if(m.config == s.config) {
connection.connector(m, s)
}else{
val tmp = cloneOf(s)
m >> tmp //Adapte the bus kind.
connection.connector(tmp,s)
}
}
}