VexRiscvSmpCluster add a few options
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fa2899a1a2
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@ -188,6 +188,31 @@ object VexRiscvSmpClusterGen {
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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assert(!(withDouble && !withFloat))
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val csrConfig = if(withSupervisor){
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CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)
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} else {
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CsrPluginConfig(
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catchIllegalAccess = true,
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mvendorid = null,
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marchid = null,
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mimpid = null,
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mhartid = 0,
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misaExtensionsInit = 0,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecInit = null,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ecallGen = true,
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wfiGenAsWait = false,
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wfiGenAsNop = true,
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ucycleAccess = CsrAccess.NONE
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)
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}
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val config = VexRiscvConfig(
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plugins = List(
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if(withMmu)new MmuPlugin(
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@ -283,7 +308,7 @@ object VexRiscvSmpClusterGen {
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mulUnrollFactor = 32,
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divUnrollFactor = 1
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),
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new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)),
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new CsrPlugin(csrConfig),
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new BranchPlugin(
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earlyBranch = earlyBranch,
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catchAddressMisaligned = true,
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