Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax

This commit is contained in:
Charles Papon 2017-07-20 14:19:34 +02:00
parent 950944e040
commit 570f0e1e3e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/VexRiscv/ip/DataCache.scala
View File

@ -419,7 +419,7 @@ class DataCache(p : DataCacheConfig) extends Component{
requestIn.valid := False
requestIn.payload.assignDontCare()
val request = requestIn.stage() //TODO FMAX half pipe ?
val request = requestIn.halfPipe()
request.ready := False
val buffer = Mem(Bits(p.memDataWidth bits),memTransactionPerLine << tagSizeShift) // WARNING << tagSizeShift could resolve cyclone II issue, //.add(new AttributeString("ramstyle","M4K"))