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VexRiscv
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Merge branch 'master' into dev 

# Conflicts:
#	build.sbt
This commit is contained in:
Dolu1990 2022-02-05 11:32:40 +01:00
parent 62c07670af 7d9a50357f
commit 5714680278
3 changed files with 8 additions and 6 deletions
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4
src/main/scala/vexriscv/demo/Linux.scala
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@ -42,13 +42,13 @@ sbt "runMain vexriscv.demo.LinuxGen -r"
cd src/test/cpp/regression
make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=yes CSR=yes DEBUG_PLUGIN=no COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=yes
Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
Run linux in simulation (Require the machine mode emulator compiled in SIM mode) =>
sbt "runMain vexriscv.demo.LinuxGen"
cd src/test/cpp/regression
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes DEBUG_PLUGIN=no COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio WITH_USER_IO=yes TRACE=no FLOW_INFO=no
Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
Run linux with QEMU (Require the machine mode emulator compiled in QEMU mode)
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=src/main/c/emulator/build/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb,addr=0xC3000000 -device loader,file=$BUILDROOT/output/images/Image,addr=0xC0000000 -device loader,file=$BUILDROOT/output/images/rootfs.cpio,addr=0xc2000000

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -689,8 +689,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
val exceptionCode = Reg(UInt(trapCodeWidth bits))
}
val mtval = Reg(UInt(xlen bits))
val mcycle = Reg(UInt(64 bits)) randBoot()
val minstret = Reg(UInt(64 bits)) randBoot()
val mcycle = Reg(UInt(64 bits)) init(0)
val minstret = Reg(UInt(64 bits)) init(0)
val medeleg = supervisorGen generate new Area {

6
src/test/cpp/regression/main.cpp
View File

@ -2752,8 +2752,10 @@ public:
virtual void preCycle(){
if ((top->dBusAvalon_read || top->dBusAvalon_write) && top->dBusAvalon_waitRequestn) {
if(top->dBusAvalon_write){
uint32_t size = __builtin_popcount(top->dBusAvalon_byteEnable);
uint32_t offset = ffs(top->dBusAvalon_byteEnable)-1;
bool error_next = false;
ws->dBusAccess(top->dBusAvalon_address + beatCounter * 4,1,2,top->dBusAvalon_byteEnable,&top->dBusAvalon_writeData,&error_next);
ws->dBusAccess(top->dBusAvalon_address + beatCounter * 4 + offset,1,size,((uint8_t*)&top->dBusAvalon_writeData)+offset,&error_next);
beatCounter++;
if(beatCounter == top->dBusAvalon_burstCount){
beatCounter = 0;
@ -2761,7 +2763,7 @@ public:
} else {
for(int beat = 0;beat < top->dBusAvalon_burstCount;beat++){
DBusCachedAvalonTask rsp;
ws->dBusAccess(top->dBusAvalon_address + beat * 4,0,2,0,&rsp.data,&rsp.error);
ws->dBusAccess(top->dBusAvalon_address + beat * 4 ,0,4,((uint8_t*)&rsp.data),&rsp.error);
rsps.push(rsp);
}
}