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VexRiscv
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Add more axi bridges

This commit is contained in:
Dolu1990 2018-02-08 21:39:22 +01:00
parent fc5d89ad03
commit 57ebfee2e6
2 changed files with 13 additions and 0 deletions
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11
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -4,8 +4,19 @@ import vexriscv.ip._
import vexriscv._ import vexriscv._
import spinal.core._ import spinal.core._
import spinal.lib._ import spinal.lib._
import spinal.lib.bus.amba4.axi.Axi4
class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null) extends DBusCachedPlugin(config, memoryTranslatorPortConfig){
var dAxi : Axi4 = null
override def build(pipeline: VexRiscv): Unit = {
super.build(pipeline)
dBus.asDirectionLess()
dAxi = master(dBus.toAxi4Shared().toAxi4()).setName("dAxi")
dBus = null //For safety, as nobody should use it anymore :)
}
}
class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null) extends Plugin[VexRiscv]{ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null) extends Plugin[VexRiscv]{
import config._ import config._

2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -103,6 +103,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
axi2 axi2
} }
def toAxi4(stageCmd : Boolean = true) = this.toAxi4Shared(stageCmd).toAxi4()
def toAvalon(stageCmd : Boolean = true): AvalonMM = { def toAvalon(stageCmd : Boolean = true): AvalonMM = {