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Add Murax fast in synthesis bench

This commit is contained in:
Dolu1990 2017-08-01 21:14:09 +02:00
parent a37494f27f
commit 58981c0e8e
1 changed files with 15 additions and 3 deletions
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18
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -20,7 +20,6 @@ object VexRiscvSynthesisBench {
SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head))
}
val smallAndProductive = new Rtl {
override def getName(): String = "VexRiscv small and productive"
override def getRtlPath(): String = "VexRiscvSmallAndProductive.v"
@ -33,7 +32,6 @@ object VexRiscvSynthesisBench {
SpinalVerilog(GenFullNoMmuNoCache.cpu().setDefinitionName(getRtlPath().split("\\.").head))
}
val fullNoMmu = new Rtl {
override def getName(): String = "VexRiscv full no MMU"
override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
@ -105,8 +103,22 @@ object MuraxSynthesisBench {
}
val muraxFast = new Rtl {
override def getName(): String = "MuraxFast"
override def getRtlPath(): String = "MuraxFast.v"
SpinalVerilog({
val murax = new Murax(MuraxConfig.default.copy(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true
)).setDefinitionName(getRtlPath().split("\\.").head)
murax.io.mainClk.setName("clk")
murax
})
}
val rtls = List(murax)
val rtls = List(murax, muraxFast)
val targets = XilinxStdTargets(
vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"