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IBusCachedPlugin move memory access outside the pipeline

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This commit is contained in:
Charles Papon 2017-04-07 13:27:47 +02:00
parent 8f09867bda
commit 5c594d6d2a
1 changed files with 10 additions and 7 deletions
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17
src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala
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@ -200,10 +200,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
}))
if(wrappedMemAccess)
io.mem.cmd.address := requestIn.addr(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit)
else
io.mem.cmd.address := requestIn.addr(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit)
val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(0)
@ -231,15 +227,21 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val request = requestIn.haltWhen(!io.mem.cmd.ready).stage()
val request = requestIn.stage()
val lineInfoWrite = new LineInfo()
lineInfoWrite.valid := flushCounter.msb
lineInfoWrite.address := request.addr(tagRange)
if(catchAccessFault) lineInfoWrite.error := loadingWithError
//Send memory requests
val memCmdSended = RegInit(False) setWhen(io.mem.cmd.fire)
io.mem.cmd.valid := request.valid && !memCmdSended
if(wrappedMemAccess)
io.mem.cmd.address := request.addr(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit)
else
io.mem.cmd.address := request.addr(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit)
io.mem.cmd.valid := requestIn.valid && !request.isStall
val wordIndex = Reg(UInt(log2Up(wordPerLine) bit))
val loadedWordsNext = Bits(wordPerLine bit)
val loadedWords = RegNext(loadedWordsNext)
@ -267,7 +269,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
}
when(requestIn.ready){
wordIndex := io.mem.cmd.address(wordRange)
memCmdSended := False
wordIndex := requestIn.addr(wordRange)
loadedWords := 0
loadedWordsReadable := 0
readyDelay := 0