Merge remote-tracking branch 'origin/linuxDev' into linux

This commit is contained in:
Charles Papon 2019-04-20 15:33:30 +02:00
commit 5cd74d2845
8 changed files with 126 additions and 47 deletions

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language: scala language: scala
dist: xenial
notifications: notifications:
email: email:
on_success: never on_success: never
# See 'project/Version.scala'
scala: scala:
- 2.11.6 - 2.11.12
sbt_args: -no-colors -J-Xss2m sbt_args: -no-colors -J-Xss2m
script: addons:
- export VEXRISCV_REGRESSION_FREERTOS_COUNT=no apt:
- export VEXRISCV_REGRESSION_THREAD_COUNT=1 sources:
- sbt -jvm-opts travis/jvmopts.compile compile - ubuntu-toolchain-r-test
- sbt -jvm-opts travis/jvmopts.test test packages:
- git
- make
- autoconf
- g++
- flex
- bison
jdk: jdk:
- oraclejdk8 - openjdk10
# - oraclejdk7
# - openjdk7
env: jobs:
- VEXRISCV_REGRESSION_CONFIG_COUNT=0 include:
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 - stage: prepare cache-verilator
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 script:
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 - cp scripts/regression/verilator.mk $HOME/makefile
- VEXRISCV_REGRESSION_CONFIG_COUNT=5 - cd $HOME
- make verilator_binary
- &test
stage: Test
name: TEST_DHRYSTONE
script:
- make regression_dhrystone -C scripts/regression
- <<: *test
stage: Test
name: TEST_BAREMETAL
script:
- make regression_random_baremetal -C scripts/regression
- <<: *test
stage: Test
name: TEST_BAREMETAL
script:
- make regression_random_baremetal -C scripts/regression
- <<: *test
stage: Test
name: TEST_MIXED
script:
- make regression_random -C scripts/regression
- <<: *test
stage: Test
name: TEST_LINUX
script:
- make regression_random_linux -C scripts/regression
- <<: *test
stage: Test
name: TEST_LINUX
script:
- make regression_random_linux -C scripts/regression
before_install: before_install:
# JDK fix
- cat /etc/hosts # optionally check the content *before*
- sudo hostname "$(hostname | cut -c1-63)"
- sed -e "s/^\\(127\\.0\\.0\\.1.*\\)/\\1 $(hostname | cut -c1-63)/" /etc/hosts | sudo tee /etc/hosts
- cat /etc/hosts # optionally check the content *after*
- cd .. - cd ..
# Verilator
- sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites
- wget https://www.veripool.org/ftp/verilator-4.012.tgz
- tar xvzf verilator*.t*gz
- cd verilator*
- ./configure
- make -j$(nproc)
- sudo make install
- cd ..
- git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev - git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
- cd VexRiscv - cd VexRiscv
- git submodule update --init --recursive - export VERILATOR_ROOT=$HOME/verilator
#- curl -T README.md -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/README.md - export PATH=$VERILATOR_ROOT/bin:$PATH
#- curl -X POST -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/publish
#- sbt compile
before_cache: before_cache:
# Tricks to avoid unnecessary cache updates - rm -fv $HOME/.ivy2/.sbt.ivy.lock
- find $HOME/.ivy2 -name "ivydata-*.properties" -delete - find $HOME/.ivy2/cache -name "ivydata-*.properties" -print -delete
- find $HOME/.sbt -name "*.lock" -delete - find $HOME/.sbt -name "*.lock" -print -delete
cache: cache:
directories: directories:
- $HOME/.ivy2/cache - $HOME/.ivy2/cache
- $HOME/.sbt/boot/ - $HOME/.sbt
- verilator-4.012 - $HOME/verilator

2
scripts/regression/.gitignore vendored Normal file
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verilator*
!verilator.mk

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.ONESHELL:
include verilator.mk
include regression.mk

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.ONESHELL:
regression_random:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_COUNT=4
export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_random_linux:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=1.0
export VEXRISCV_REGRESSION_CONFIG_COUNT=3
export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_random_baremetal:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0
export VEXRISCV_REGRESSION_CONFIG_COUNT=50
export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_dhrystone:
cd ../..
sbt "testOnly vexriscv.DhrystoneBench"

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.ONESHELL:
verilator/configure:
rm -rf verilator*
wget https://www.veripool.org/ftp/verilator-4.012.tgz
tar xvzf verilator*.t*gz
mv verilator-4.012 verilator
verilator/Makefile: verilator/configure
cd verilator
./configure
verilator/bin/verilator_bin: verilator/Makefile
cd verilator
make -j$(shell nproc)
rm -rf src/obj_dbg
rm -rf src/obj_opt
verilator_binary: verilator/bin/verilator_bin

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@ -3680,7 +3680,7 @@ int main(int argc, char **argv, char **env) {
redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3);); redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
#endif #endif
#ifdef DBUS_CACHED #ifdef DBUS_CACHED
redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(500e3);); redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(2500e3););
#endif #endif
#ifdef MMU #ifdef MMU

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@ -75,7 +75,7 @@ object MuraxSim {
}) })
setAlignmentX(awt.Component.CENTER_ALIGNMENT) setAlignmentX(awt.Component.CENTER_ALIGNMENT)
}) })
setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE) setDefaultCloseOperation(WindowConstants.EXIT_ON_CLOSE)
pack() pack()
setVisible(true) setVisible(true)

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@ -585,10 +585,11 @@ class TestIndividualFeatures extends FunSuite {
println(s"Seed=$seed") println(s"Seed=$seed")
for(i <- 0 until sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt){ for(i <- 0 until sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt){
var positions : List[VexRiscvPosition] = null var positions : List[VexRiscvPosition] = null
val universe = VexRiscvUniverse.universes.filter(e => rand.nextBoolean()) var universe = mutable.HashSet[VexRiscvUniverse]()
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.5").toDouble > Math.random()) universe += VexRiscvUniverse.CATCH_ALL
do{ do{
positions = dimensions.map(d => d.randomPosition(universe, rand)) positions = dimensions.map(d => d.randomPosition(universe.toList, rand))
}while(!positions.forall(_.isCompatibleWith(positions))) }while(!positions.forall(_.isCompatibleWith(positions)))
val testSeed = rand.nextInt() val testSeed = rand.nextInt()