Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register
(used to inject instruction from the debug plugin)
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b65ef189eb
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5df56bea79
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@ -22,7 +22,8 @@ case class InstructionCacheConfig( cacheSize : Int,
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asyncTagMemory : Boolean,
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twoCycleCache : Boolean = true,
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twoCycleRam : Boolean = false,
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preResetFlush : Boolean = false){
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preResetFlush : Boolean = false,
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bypassGen : Boolean = false ){
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assert(!(twoCycleRam && !twoCycleCache))
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@ -108,8 +109,8 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
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val isRemoved = Bool()
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val pc = UInt(p.addressWidth bits)
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val data = Bits(p.cpuDataWidth bits)
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val dataBypassValid = Bool()
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val dataBypass = Bits(p.cpuDataWidth bits)
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val dataBypassValid = p.bypassGen generate Bool()
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val dataBypass = p.bypassGen generate Bits(p.cpuDataWidth bits)
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val mmuBus = MemoryTranslatorBus()
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val physicalAddress = UInt(p.addressWidth bits)
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val cacheMiss, error, mmuRefilling, mmuException, isUser = ifGen(!p.twoCycleCache)(Bool)
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@ -415,15 +416,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val id = OHToUInt(hits)
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val error = read.waysValues.map(_.tag.error).read(id)
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val data = read.waysValues.map(_.data).read(id)
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val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
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io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word)
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val word = if(cpuDataWidth == memDataWidth) CombInit(data) else data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
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io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word) else word)
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if(twoCycleCache){
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io.cpu.decode.data := RegNextWhen(io.cpu.fetch.data,!io.cpu.decode.isStuck)
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}
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}
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if(twoCycleRam && wayCount == 1){
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io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)))
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val cacheData = if(cpuDataWidth == memDataWidth) CombInit(read.waysValues.head.data) else read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
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io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | cacheData) else cacheData)
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}
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io.cpu.fetch.mmuBus.cmd.isValid := io.cpu.fetch.isValid
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@ -458,8 +460,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val id = OHToUInt(hits)
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val error = tags(id).error
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val data = fetchStage.read.waysValues.map(way => stage(way.data)).read(id)
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val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange))
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when(stage(io.cpu.fetch.dataBypassValid)){
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val word = if(cpuDataWidth == memDataWidth) data else data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange))
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if(p.bypassGen) when(stage(io.cpu.fetch.dataBypassValid)){
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word := stage(io.cpu.fetch.dataBypass)
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}
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io.cpu.decode.data := word
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@ -61,7 +61,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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var redoBranch : Flow[UInt] = null
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var decodeExceptionPort : Flow[ExceptionCause] = null
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val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]()
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def tightlyGen = tightlyCoupledPorts.nonEmpty
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def newTightlyCoupledPort(p : TightlyCoupledPortParameter) = {
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val port = TightlyCoupledPort(p, null)
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@ -125,7 +125,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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import pipeline.config._
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pipeline plug new FetchArea(pipeline) {
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val cache = new InstructionCache(IBusCachedPlugin.this.config)
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val cache = new InstructionCache(IBusCachedPlugin.this.config.copy(bypassGen = tightlyGen))
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iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
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iBus <> cache.io.mem
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iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
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@ -165,8 +165,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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val tightlyCoupledHits = RegNextWhen(s0.tightlyCoupledHits, stages(1).input.ready)
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val tightlyCoupledHit = RegNextWhen(s0.tightlyCoupledHit, stages(1).input.ready)
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cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit
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cache.io.cpu.fetch.dataBypass := (if(tightlyCoupledPorts.isEmpty) B(0) else MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data))))
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if(tightlyGen) cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit
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if(tightlyGen) cache.io.cpu.fetch.dataBypass := MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data)))
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//Connect fetch cache side
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cache.io.cpu.fetch.isValid := stages(1).input.valid && !tightlyCoupledHit
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