Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

BmbInterconnectGenerator refractoring

This commit is contained in:
Dolu1990 2020-07-15 17:03:05 +02:00
parent 4f5ba6b044
commit 5f0aec7570
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
View File

@ -1,7 +1,7 @@
package vexriscv package vexriscv
import spinal.core._ import spinal.core._
import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbImplicitDebugDecoder, BmbInvalidationParameter, BmbParameter, BmbSmpInterconnectGenerator} import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbImplicitDebugDecoder, BmbInvalidationParameter, BmbParameter, BmbInterconnectGenerator}
import spinal.lib.bus.misc.AddressMapping import spinal.lib.bus.misc.AddressMapping
import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl} import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
import spinal.lib.generator._ import spinal.lib.generator._
@ -17,7 +17,7 @@ object VexRiscvBmbGenerator{
val DEBUG_BMB = 4 val DEBUG_BMB = 4
} }
case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbSmpInterconnectGenerator = null) extends Generator { case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGenerator = null) extends Generator {
import VexRiscvBmbGenerator._ import VexRiscvBmbGenerator._
val config = Handle[VexRiscvConfig] val config = Handle[VexRiscvConfig]

4
src/main/scala/vexriscv/demo/smp/Misc.scala
View File

@ -247,7 +247,7 @@ object BmbToLiteDramTester extends App{
} }
} }
case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbSmpInterconnectGenerator) extends Generator{ case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Generator{
val liteDramParameter = createDependency[LiteDramNativeParameter] val liteDramParameter = createDependency[LiteDramNativeParameter]
val bmb = produce(logic.io.input) val bmb = produce(logic.io.input)
val dram = produceIo(logic.io.output) val dram = produceIo(logic.io.output)
@ -269,7 +269,7 @@ case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnec
) )
} }
case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbSmpInterconnectGenerator) extends Generator{ case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Generator{
val bmb = produce(logic.io.input) val bmb = produce(logic.io.input)
val wishbone = produce(logic.io.output) val wishbone = produce(logic.io.output)

2
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -37,7 +37,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{
this.onClockDomain(systemCd.outputClockDomain) this.onClockDomain(systemCd.outputClockDomain)
implicit val interconnect = BmbSmpInterconnectGenerator() implicit val interconnect = BmbInterconnectGenerator()
val debugBridge = JtagInstructionDebuggerGenerator() onClockDomain(debugCd.outputClockDomain) val debugBridge = JtagInstructionDebuggerGenerator() onClockDomain(debugCd.outputClockDomain)
debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false)) debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))