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VexRiscv
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Handle `ERR` in `toWishbone`

This commit is contained in:
Martijn Bastiaan 2024-03-22 21:24:32 +01:00
parent 6aeb6d4d43
commit 5f58e0c7c6
4 changed files with 13 additions and 13 deletions
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6
src/main/scala/vexriscv/ip/DataCache.scala
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@ -368,13 +368,13 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
bus.WE := cmdBridge.wr bus.WE := cmdBridge.wr
bus.DAT_MOSI := cmdBridge.data bus.DAT_MOSI := cmdBridge.data
cmdBridge.ready := cmdBridge.valid && bus.ACK cmdBridge.ready := cmdBridge.valid && (bus.ACK || bus.ERR)
bus.CYC := cmdBridge.valid bus.CYC := cmdBridge.valid
bus.STB := cmdBridge.valid bus.STB := cmdBridge.valid
rsp.valid := RegNext(cmdBridge.valid && !bus.WE && bus.ACK) init(False) rsp.valid := RegNext(cmdBridge.valid && !bus.WE && (bus.ACK || bus.ERR)) init(False)
rsp.data := RegNext(bus.DAT_MISO) rsp.data := RegNext(bus.DAT_MISO)
rsp.error := False //TODO rsp.error := RegNext(bus.ERR)
bus bus
} }

8
src/main/scala/vexriscv/ip/InstructionCache.scala
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@ -239,15 +239,15 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
when(cmd.valid || pending){ when(cmd.valid || pending){
bus.CYC := True bus.CYC := True
bus.STB := True bus.STB := True
when(bus.ACK){ when(bus.ACK || bus.ERR){
counter := counter + 1 counter := counter + 1
} }
} }
cmd.ready := cmd.valid && bus.ACK cmd.ready := cmd.valid && (bus.ACK || bus.ERR)
rsp.valid := RegNext(bus.CYC && bus.ACK) init(False) rsp.valid := RegNext(bus.CYC && (bus.ACK || bus.ERR)) init(False)
rsp.data := RegNext(bus.DAT_MISO) rsp.data := RegNext(bus.DAT_MISO)
rsp.error := False //TODO rsp.error := RegNext(bus.ERR)
bus bus
} }

6
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -199,13 +199,13 @@ case class DBusSimpleBus(bigEndian : Boolean = false) extends Bundle with IMaste
bus.WE := cmdStage.wr bus.WE := cmdStage.wr
bus.DAT_MOSI := cmdStage.data bus.DAT_MOSI := cmdStage.data
cmdStage.ready := cmdStage.valid && bus.ACK cmdStage.ready := cmdStage.valid && (bus.ACK || bus.ERR)
bus.CYC := cmdStage.valid bus.CYC := cmdStage.valid
bus.STB := cmdStage.valid bus.STB := cmdStage.valid
rsp.ready := cmdStage.valid && !bus.WE && bus.ACK rsp.ready := cmdStage.valid && !bus.WE && (bus.ACK || bus.ERR)
rsp.data := bus.DAT_MISO rsp.data := bus.DAT_MISO
rsp.error := False //TODO rsp.error := bus.ERR
bus bus
} }

6
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -156,10 +156,10 @@ case class IBusSimpleBus(plugin: IBusSimplePlugin) extends Bundle with IMasterSl
bus.STB := cmdPipe.valid bus.STB := cmdPipe.valid
cmdPipe.ready := cmdPipe.valid && bus.ACK cmdPipe.ready := cmdPipe.valid && (bus.ACK || bus.ERR)
rsp.valid := bus.CYC && bus.ACK rsp.valid := bus.CYC && (bus.ACK || bus.ERR)
rsp.inst := bus.DAT_MISO rsp.inst := bus.DAT_MISO
rsp.error := False //TODO rsp.error := bus.ERR
bus bus
} }