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Briey revert RVC unwanted addition

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Dolu1990 2021-09-22 15:01:08 +02:00
parent b807254759
commit 5f5f4afbf2
1 changed files with 43 additions and 47 deletions
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90
src/main/scala/vexriscv/demo/Briey.scala
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@ -51,56 +51,52 @@ object BrieyConfig{
), ),
cpuPlugins = ArrayBuffer( cpuPlugins = ArrayBuffer(
new PcManagerSimplePlugin(0x80000000l, false), new PcManagerSimplePlugin(0x80000000l, false),
new IBusSimplePlugin( // new IBusSimplePlugin(
// interfaceKeepData = false,
// catchAccessFault = true
// ),
new IBusCachedPlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
cmdForkOnSecondStage = false, prediction = STATIC,
cmdForkPersistence = true, config = InstructionCacheConfig(
catchAccessFault = true, cacheSize = 4096,
compressedGen = true bytePerLine =32,
), wayCount = 1,
// new IBusCachedPlugin( addressWidth = 32,
// resetVector = 0x80000000l, cpuDataWidth = 32,
// prediction = STATIC, memDataWidth = 32,
// compressedGen = true, catchIllegalAccess = true,
// config = InstructionCacheConfig( catchAccessFault = true,
// cacheSize = 4096, asyncTagMemory = false,
// bytePerLine =32, twoCycleRam = true,
// wayCount = 1, twoCycleCache = true
// addressWidth = 32, )
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchIllegalAccess = true,
// catchAccessFault = true,
// asyncTagMemory = false,
// twoCycleRam = true,
// twoCycleCache = true
// )
// askMemoryTranslation = true, // askMemoryTranslation = true,
// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// portTlbSize = 4 // portTlbSize = 4
// ) // )
// ), ),
new DBusSimplePlugin( // new DBusSimplePlugin(
catchAddressMisaligned = true, // catchAddressMisaligned = true,
catchAccessFault = true // catchAccessFault = true
), // ),
// new DBusCachedPlugin( new DBusCachedPlugin(
// config = new DataCacheConfig( config = new DataCacheConfig(
// cacheSize = 4096, cacheSize = 4096,
// bytePerLine = 32, bytePerLine = 32,
// wayCount = 1, wayCount = 1,
// addressWidth = 32, addressWidth = 32,
// cpuDataWidth = 32, cpuDataWidth = 32,
// memDataWidth = 32, memDataWidth = 32,
// catchAccessError = true, catchAccessError = true,
// catchIllegal = true, catchIllegal = true,
// catchUnaligned = true catchUnaligned = true
// ), ),
// memoryTranslatorPortConfig = null memoryTranslatorPortConfig = null
// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig( // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// // portTlbSize = 6 // portTlbSize = 6
// // ) // )
// ), ),
new StaticMemoryTranslatorPlugin( new StaticMemoryTranslatorPlugin(
ioRange = _(31 downto 28) === 0xF ioRange = _(31 downto 28) === 0xF
), ),
@ -108,7 +104,7 @@ object BrieyConfig{
catchIllegalInstruction = true catchIllegalInstruction = true
), ),
new RegFilePlugin( new RegFilePlugin(
regFileReadyKind = plugin.ASYNC, regFileReadyKind = plugin.SYNC,
zeroBoot = false zeroBoot = false
), ),
new IntAluPlugin, new IntAluPlugin,
@ -204,7 +200,7 @@ class Briey(config: BrieyConfig) extends Component{
val resetCtrl = new ClockingArea(resetCtrlClockDomain) { val resetCtrl = new ClockingArea(resetCtrlClockDomain) {
val systemResetUnbuffered = False val systemResetUnbuffered = False
// val coreResetUnbuffered = False // val coreResetUnbuffered = False
//Implement an counter to keep the reset axiResetOrder high 64 cycles //Implement an counter to keep the reset axiResetOrder high 64 cycles
// Also this counter will automaticly do a reset when the system boot. // Also this counter will automaticly do a reset when the system boot.