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Fix FPU with F64 support, not removing mantissa precision from F32 #317

This commit is contained in:
Dolu1990 2023-03-01 13:56:25 +01:00
parent 6f76a45e7d
commit 5f67075e30
1 changed files with 6 additions and 1 deletions
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7
src/main/scala/vexriscv/ip/fpu/FpuCore.scala
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@ -1688,7 +1688,12 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
port.valid := input.valid && input.write port.valid := input.valid && input.write
port.address := input.source @@ input.rd port.address := input.source @@ input.rd
port.data.value := input.value port.data.value := input.value
if(p.withDouble) port.data.boxed := input.format === FpuFormat.FLOAT if(p.withDouble) {
port.data.boxed := input.format === FpuFormat.FLOAT
when(port.data.boxed){
port.data.value.mantissa(p.internalMantissaSize-23-1 downto 0) := 0
}
}
val randomSim = p.sim generate (in UInt(p.internalMantissaSize bits)) val randomSim = p.sim generate (in UInt(p.internalMantissaSize bits))
if(p.sim) when(port.data.value.isZero || port.data.value.isInfinity){ if(p.sim) when(port.data.value.isZero || port.data.value.isInfinity){