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Fix typo

This commit is contained in:
Dolu1990 2018-05-24 14:04:50 +02:00
parent 9815763b7f
commit 6004dcc365
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -154,7 +154,7 @@ object MuraxSynthesisBench {
override def getName(): String = "Murax" override def getName(): String = "Murax"
override def getRtlPath(): String = "Murax.v" override def getRtlPath(): String = "Murax.v"
SpinalVerilog({ SpinalVerilog({
val murax = new Murax(MuraxConfig.defsbault).setDefinitionName(getRtlPath().split("\\.").head) val murax = new Murax(MuraxConfig.default).setDefinitionName(getRtlPath().split("\\.").head)
murax.io.mainClk.setName("clk") murax.io.mainClk.setName("clk")
murax murax
}) })