rework i$ flush
This commit is contained in:
parent
f5d4e745c7
commit
60a41bfc75
|
@ -249,7 +249,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
|
||||||
import p._
|
import p._
|
||||||
assert(cpuDataWidth == memDataWidth, "Need testing")
|
assert(cpuDataWidth == memDataWidth, "Need testing")
|
||||||
val io = new Bundle{
|
val io = new Bundle{
|
||||||
val flush = slave(InstructionCacheFlushBus())
|
val flush = in Bool()
|
||||||
val cpu = slave(InstructionCacheCpuBus(p))
|
val cpu = slave(InstructionCacheCpuBus(p))
|
||||||
val mem = master(InstructionCacheMemBus(p))
|
val mem = master(InstructionCacheMemBus(p))
|
||||||
}
|
}
|
||||||
|
@ -300,15 +300,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
|
||||||
val valid = RegInit(False) clearWhen(fire)
|
val valid = RegInit(False) clearWhen(fire)
|
||||||
val address = Reg(UInt(addressWidth bits))
|
val address = Reg(UInt(addressWidth bits))
|
||||||
val hadError = RegInit(False) clearWhen(fire)
|
val hadError = RegInit(False) clearWhen(fire)
|
||||||
|
val flushPending = RegInit(True)
|
||||||
|
|
||||||
when(io.cpu.fill.valid){
|
when(io.cpu.fill.valid){
|
||||||
valid := True
|
valid := True
|
||||||
address := io.cpu.fill.payload
|
address := io.cpu.fill.payload
|
||||||
}
|
}
|
||||||
|
|
||||||
io.cpu.prefetch.haltIt setWhen(valid)
|
io.cpu.prefetch.haltIt setWhen(valid || flushPending)
|
||||||
|
|
||||||
val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(if(preResetFlush) wayLineCount else 0)
|
val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit))
|
||||||
when(!flushCounter.msb){
|
when(!flushCounter.msb){
|
||||||
io.cpu.prefetch.haltIt := True
|
io.cpu.prefetch.haltIt := True
|
||||||
flushCounter := flushCounter + 1
|
flushCounter := flushCounter + 1
|
||||||
|
@ -316,17 +317,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
|
||||||
when(!RegNext(flushCounter.msb)){
|
when(!RegNext(flushCounter.msb)){
|
||||||
io.cpu.prefetch.haltIt := True
|
io.cpu.prefetch.haltIt := True
|
||||||
}
|
}
|
||||||
val flushFromInterface = RegInit(False)
|
|
||||||
io.flush.cmd.ready := !(valid || io.cpu.fetch.isValid) //io.cpu.fetch.isValid will avoid bug on first cycle miss
|
when(io.flush){
|
||||||
when(io.flush.cmd.valid){
|
|
||||||
io.cpu.prefetch.haltIt := True
|
io.cpu.prefetch.haltIt := True
|
||||||
when(io.flush.cmd.ready){
|
flushPending := True
|
||||||
flushCounter := 0
|
|
||||||
flushFromInterface := True
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
io.flush.rsp := flushCounter.msb.rise && flushFromInterface
|
when(flushPending && !(valid || io.cpu.fetch.isValid) ){
|
||||||
|
flushCounter := 0
|
||||||
|
flushPending := False
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -242,19 +242,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
|
||||||
cache.io.cpu.fetch.mmuBus.rsp.refilling := False
|
cache.io.cpu.fetch.mmuBus.rsp.refilling := False
|
||||||
}
|
}
|
||||||
|
|
||||||
val flushStage = if(memory != null) memory else execute
|
val flushStage = decode
|
||||||
flushStage plug new Area {
|
cache.io.flush := flushStage.arbitration.isValid && flushStage.input(FLUSH_ALL)
|
||||||
import flushStage._
|
|
||||||
|
|
||||||
cache.io.flush.cmd.valid := False
|
|
||||||
when(arbitration.isValid && input(FLUSH_ALL)) {
|
|
||||||
cache.io.flush.cmd.valid := True
|
|
||||||
|
|
||||||
when(!cache.io.flush.cmd.ready) {
|
|
||||||
arbitration.haltItself := True
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue