fpu got exception flag right for add/sub/mul/i2f/f2i
This commit is contained in:
Dolu1990
parent
936e5823dc
commit
6170243283
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@ -451,6 +451,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val recoded = CombInit(input.rs1)
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val flag = io.port(input.source).completion.flag
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val halt = False
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val recodedResult = Bits(32 bits)//recoded.asBits.resize(32 bits)
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@ -522,6 +523,10 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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is(FpuFloat.NAN){
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recodedResult(23, 8 bits).setAll()
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when(input.rs1.isCanonical){
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recodedResult(31) := False
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recodedResult(0, 22 bits) := 0
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}
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}
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}
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}
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@ -540,8 +545,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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FpuRoundMode.RMM -> (round(1))
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)
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val result = (Mux(resign, ~unsigned, unsigned) + (resign ^ increment).asUInt)
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val overflow = RegNext((input.rs1.exponent > (input.arg(0) ? U(exponentOne+30) | U(exponentOne+31)) || input.rs1.isInfinity) && !input.rs1.sign || input.rs1.isNan)
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val underflow = RegNext((input.rs1.exponent > U(exponentOne+30) || !input.arg(0) || input.rs1.isInfinity) && input.rs1.sign)
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val overflow = (input.rs1.exponent > (input.arg(0) ? U(exponentOne+30) | U(exponentOne+31)) || input.rs1.isInfinity) && !input.rs1.sign || input.rs1.isNan
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val underflow = (input.rs1.exponent > U(exponentOne+31) || input.arg(0) && unsigned.msb && unsigned(30 downto 0) =/= 0 || !input.arg(0) && (unsigned =/= 0 || increment) || input.rs1.isInfinity) && input.rs1.sign
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val isZero = input.rs1.isZero
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when(isZero){
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result := 0
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@ -549,6 +554,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val low = overflow
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val high = input.arg(0) ^ overflow
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result := (31 -> high, default -> low)
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flag.NV := input.valid && input.opcode === FpuOpcode.F2I && fsm.done && !isZero
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}
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}
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@ -648,8 +654,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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scrap setWhen(needShift && mulHigh(0))
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val forceZero = input.rs1.isZero || input.rs2.isZero
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val forceUnderflow = exp < exponentOne + exponentOne - 127 - 24 // 0x6A //TODO
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val forceOverflow = /*exp > exponentOne + exponentOne + 127 || */input.rs1.isInfinity || input.rs2.isInfinity
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val forceNan = input.rs1.isNan || input.rs2.isNan || ((input.rs1.isInfinity || input.rs2.isInfinity) && (input.rs1.isZero || input.rs2.isZero))
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val forceOverflow = input.rs1.isInfinity || input.rs2.isInfinity
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val infinitynan = ((input.rs1.isInfinity || input.rs2.isInfinity) && (input.rs1.isZero || input.rs2.isZero))
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val forceNan = input.rs1.isNan || input.rs2.isNan || infinitynan
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val output = p.writeFloating()
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output.sign := input.rs1.sign ^ input.rs2.sign
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@ -657,8 +664,10 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.mantissa := man.asUInt
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output.setNormal
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val flag = io.port(input.source).completion.flag
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when(forceNan) {
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output.setNanQuiet
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flag.NV setWhen(input.valid && (infinitynan || input.rs1.isNanSignaling || input.rs2.isNanSignaling))
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} elsewhen(forceOverflow) {
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output.setInfinity
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} elsewhen(forceZero) {
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@ -936,7 +945,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val forceZero = xyMantissa === 0 || (input.rs1.isZero && input.rs2.isZero)
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// val forceOverflow = exponent === exponentOne + 128 //Handled by writeback rounding
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val forceInfinity = (input.rs1.isInfinity || input.rs2.isInfinity)
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val forceNan = input.rs1.isNan || input.rs2.isNan || (input.rs1.isInfinity && input.rs2.isInfinity && (input.rs1.sign ^ input.rs2.sign))
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val infinityNan = (input.rs1.isInfinity && input.rs2.isInfinity && (input.rs1.sign ^ input.rs2.sign))
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val forceNan = input.rs1.isNan || input.rs2.isNan || infinityNan
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}
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@ -951,6 +961,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.roundMode := input.roundMode
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output.scrap := (norm.mantissa(1) | norm.mantissa(0) | shifter.roundingScrap)
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val flag = io.port(input.source).completion.flag
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flag.NV setWhen(input.valid && (norm.infinityNan || input.rs1.isNanSignaling || input.rs2.isNanSignaling))
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when(norm.forceNan) {
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output.value.setNanQuiet
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} elsewhen(norm.forceZero) {
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@ -963,21 +976,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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} elsewhen(norm.forceInfinity) {
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output.value.setInfinity
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} /*elsewhen(norm.forceOverflow) {
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val doMax = input.roundMode.mux(
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FpuRoundMode.RNE -> (False),
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FpuRoundMode.RTZ -> (True),
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FpuRoundMode.RDN -> (!output.value.sign),
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FpuRoundMode.RUP -> (output.value.sign),
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FpuRoundMode.RMM -> (False)
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)
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when(doMax){
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output.value.exponent := exponentOne + 127
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output.value.mantissa.setAll()
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} otherwise {
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output.value.setInfinity
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}
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}*/
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}
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@ -993,8 +992,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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//TODO do not break NAN payload (seems already fine)
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val manAggregate = input.value.mantissa @@ input.scrap
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val expDif = (exponentOne-126) - input.value.exponent
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val discardCount = expDif.msb ? U(0) | expDif.resize(log2Up(p.internalMantissaSize) bits)
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val expDif = (exponentOne-126) -^ input.value.exponent
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val expSubnormal = !expDif.msb
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val discardCount = expSubnormal ? expDif.resize(log2Up(p.internalMantissaSize) bits) | U(0)
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val exactMask = (List(True) ++ (0 until p.internalMantissaSize+1).map(_ < discardCount)).asBits.asUInt
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val roundAdjusted = (True ## (manAggregate>>1))(discardCount) ## ((manAggregate & exactMask) =/= 0)
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@ -1017,8 +1017,18 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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math.mantissa := adder(0, p.internalMantissaSize bits)
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val patched = CombInit(math)
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val nx,of,uf = False
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// val ufPatch = input.roundMode === FpuRoundMode.RUP && !input.value.sign && !input.scrap|| input.roundMode === FpuRoundMode.RDN && input.value.sign && !input.scrap
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// when(!math.special && (input.value.exponent <= exponentOne-127 && (math.exponent =/= exponentOne-126 || !input.value.mantissa.lsb || ufPatch)) && roundAdjusted.asUInt =/= 0){
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// uf := True
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// }
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when(!math.special && math.exponent <= exponentOne-127 && roundAdjusted.asUInt =/= 0){ //Do not catch exact 1.17549435E-38 underflow, but, who realy care ?
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uf := True
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}
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when(!math.special && math.exponent >= exponentOne + 128){
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// patched.setInfinity
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nx := True
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of := True
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val doMax = input.roundMode.mux(
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FpuRoundMode.RNE -> (False),
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FpuRoundMode.RTZ -> (True),
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@ -1036,6 +1046,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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when(!math.special && math.exponent <= exponentOne - 127-23){
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nx := True
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uf := True
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val doMin = input.roundMode.mux(
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FpuRoundMode.RNE -> (False),
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FpuRoundMode.RTZ -> (False),
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@ -1051,6 +1063,14 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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}
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nx setWhen(!input.value.special && (roundAdjusted =/= 0))
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when(input.valid){
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val flag = io.port(input.source).completion.flag
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flag.NX setWhen(nx)
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flag.OF setWhen(of)
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flag.UF setWhen(uf)
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}
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val output = input.swapPayload(RoundOutput())
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output.source := input.source
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output.lockId := input.lockId
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@ -1079,8 +1099,11 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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if(p.sim) when(port.data.isZero || port.data.isInfinity){
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port.data.mantissa.assignDontCare()
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}
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if(p.sim) when(port.data.special){
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port.data.exponent(p.internalExponentSize-1 downto 2).assignDontCare()
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if(p.sim) when(input.value.special){
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port.data.exponent(p.internalExponentSize-1 downto 3).assignDontCare()
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when(!input.value.isNan){
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port.data.exponent(2 downto 2).assignDontCare()
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}
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}
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when(port.valid){
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@ -27,6 +27,7 @@ object FpuFloat{
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val ZERO = 0
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val INFINITY = 1
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val NAN = 2
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val NAN_CANONICAL_BIT = 2
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}
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case class FpuFloat(exponentSize: Int,
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@ -49,12 +50,14 @@ case class FpuFloat(exponentSize: Int,
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def isInfinity = special && exponent(1 downto 0) === FpuFloat.INFINITY
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def isNan = special && exponent(1 downto 0) === FpuFloat.NAN
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def isQuiet = mantissa.msb
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def isNanSignaling = special && exponent(1 downto 0) === FpuFloat.NAN && !isQuiet
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def isCanonical = exponent(FpuFloat.NAN_CANONICAL_BIT)
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def setNormal = { special := False }
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def setZero = { special := True; exponent(1 downto 0) := FpuFloat.ZERO }
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def setInfinity = { special := True; exponent(1 downto 0) := FpuFloat.INFINITY }
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def setNan = { special := True; exponent(1 downto 0) := FpuFloat.NAN }
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def setNanQuiet = { special := True; exponent(1 downto 0) := FpuFloat.NAN ; mantissa.msb := True }
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def setNan = { special := True; exponent(1 downto 0) := FpuFloat.NAN; exponent(FpuFloat.NAN_CANONICAL_BIT) := False}
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def setNanQuiet = { special := True; exponent(1 downto 0) := FpuFloat.NAN; exponent(FpuFloat.NAN_CANONICAL_BIT) := True; mantissa.msb := True; }
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def decode() = {
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val ret = FpuFloatDecoded()
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@ -23,7 +23,7 @@ import scala.util.Random
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class FpuTest extends FunSuite{
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val b2f = lang.Float.intBitsToFloat(_)
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val f2b = lang.Float.floatToIntBits(_)
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val f2b = lang.Float.floatToRawIntBits(_)
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def clamp(f : Float) = {
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f // if(f.abs < b2f(0x00800000)) b2f(f2b(f) & 0x80000000) else f
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@ -38,9 +38,11 @@ class FpuTest extends FunSuite{
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)
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val config = SimConfig
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// config.withFstWave
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config.allOptimisation
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config.withFstWave
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config.compile(new FpuCore(portCount, p){
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for(i <- 0 until portCount) out(Bits(5 bits)).setName(s"flagAcc$i") := io.port(i).completion.flag.asBits
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setDefinitionName("FpuCore")
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}).doSim(seed = 42){ dut =>
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dut.clockDomain.forkStimulus(10)
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dut.clockDomain.forkSimSpeedPrinter(5.0)
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@ -48,10 +50,29 @@ class FpuTest extends FunSuite{
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class TestCase(op : String){
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def build(arg : String) = new ProcessStream(s"testfloat_gen $arg -forever -$op"){
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def f32_2 ={
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def build(arg : String) = new ProcessStream(s"testfloat_gen $arg -tininessafter -forever -$op"){
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def f32_f32 ={
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val s = new Scanner(next)
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(b2f(s.nextLong(16).toInt), b2f(s.nextLong(16).toInt), b2f(s.nextLong(16).toInt), s.nextInt(16))
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val a,b,c = (s.nextLong(16).toInt)
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// if(b2f(a).isNaN || b2f(b).isNaN){
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// print("NAN => ")
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// if(((a >> 23) & 0xFF) == 0xFF && ((a >> 0) & 0xEFFFFF) != 0){
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// print(a.toHexString)
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// print(" " + f2b(b2f(a)).toHexString)
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// }
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// if(((b >> 23) & 0xFF) == 0xFF && ((b >> 0) & 0xEFFFFF) != 0){
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// print(b.toHexString)
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// print(" " + f2b(b2f(b)).toHexString)
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// }
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// if(((c >> 23) & 0xFF) == 0xFF && ((c >> 0) & 0xEFFFFF) != 0){
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// print(" " + c.toHexString)
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// print(" " + f2b(b2f(c)).toHexString)
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// }
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//
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// print(" " + simTime())
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// println("")
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// }
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(b2f(a), b2f(b), b2f(c), s.nextInt(16))
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}
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def i32_f32 ={
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@ -95,18 +116,26 @@ class FpuTest extends FunSuite{
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val commitQueue = mutable.Queue[FpuCommit => Unit]()
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val rspQueue = mutable.Queue[FpuRsp => Unit]()
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var pending = 0
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var pendingMiaou = 0
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var flagAccumulator = 0
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def cmdAdd(body : FpuCmd => Unit): Unit ={
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pending += 1
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pendingMiaou += 1
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cmdQueue += body
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}
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def softAssert(cond : Boolean, msg : String) = if(!cond)println(msg)
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def flagMatch(ref : Int, value : Float, report : String): Unit ={
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waitUntil(pendingMiaou == 0)
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val patch = if(value.abs == 1.17549435E-38f) ref & ~2 else ref
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assert(flagAccumulator == patch, s"Flag missmatch dut=$flagAccumulator ref=$patch $report")
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flagAccumulator = 0
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}
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val flagAggregated = dut.reflectBaseType(s"flagAcc$id").asInstanceOf[Bits]
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dut.clockDomain.onSamplings{
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val c = dut.io.port(id).completion
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pending -= c.count.toInt
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pendingMiaou -= c.count.toInt
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flagAccumulator |= flagAggregated.toInt
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}
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@ -152,7 +181,7 @@ class FpuTest extends FunSuite{
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}
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def load(rd : Int, value : Float): Unit ={
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loadRaw(rd, lang.Float.floatToIntBits(value).toLong & 0xFFFFFFFFl)
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loadRaw(rd, f2b(value).toLong & 0xFFFFFFFFl)
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}
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def storeRaw(rs : Int)(body : FpuRsp => Unit): Unit ={
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@ -166,7 +195,7 @@ class FpuTest extends FunSuite{
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}
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rspQueue += body
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waitUntil(rspQueue.isEmpty)
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// waitUntil(rspQueue.isEmpty)
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}
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def storeFloat(rs : Int)(body : Float => Unit): Unit ={
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@ -385,6 +414,9 @@ class FpuTest extends FunSuite{
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storeFloat(rd){v =>
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assert(f2b(v) == f2b(ref), f"## ${a} ${opName} $b = $v, $ref $rounding")
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}
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flagMatch(flag, ref, f"## ${opName} ${a} $b $ref $rounding")
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}
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def testAddExact(a : Float, b : Float, ref : Float, flag : Int, rounding : FpuRoundMode.E): Unit ={
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@ -538,6 +570,8 @@ class FpuTest extends FunSuite{
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assert(v == ref2, f" <= f2ui($a) = $v, $ref2, $rounding $flag")
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}
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}
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flagMatch(flag, ref, f" f2${if(signed) "" else "u"}i($a) $ref $flag $rounding")
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}
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@ -563,6 +597,9 @@ class FpuTest extends FunSuite{
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val ref = b
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assert(f2b(v) == f2b(ref), f"i2f($aLong) = $v, $ref")
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}
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flagMatch(f, b, f"i2f() = $b")
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}
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@ -589,7 +626,7 @@ class FpuTest extends FunSuite{
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val rd = Random.nextInt(32)
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load(rs1, a)
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fmv_x_w(rs1){rsp =>
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val ref = lang.Float.floatToIntBits(a).toLong & 0xFFFFFFFFl
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val ref = f2b(a).toLong & 0xFFFFFFFFl
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val v = rsp.value.toBigInt
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println(f"fmv_x_w $a = $v, $ref")
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assert(v === ref)
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@ -682,48 +719,16 @@ class FpuTest extends FunSuite{
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val binaryOps = List[(Int,Int,Int,FpuRoundMode.E) => Unit](add, sub, mul)
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testI2f(24, false)
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testI2f(17, false)
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testLoadStore(2.5f)
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testLoadStore(3.67341984632e-40f)
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testLoadStore(5.5321021294e-40f)
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testF2iExact(-2.14748365E9f, -2147483648, 0, true, FpuRoundMode.RDN)
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for(_ <- 0 until 100000){
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val rounding = FpuRoundMode.elements.randomPick()
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val (a,b,c,f) = f32.add(rounding).f32_2
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testBinaryOp(add,a,b,c,f, rounding,"add")
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}
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for(_ <- 0 until 100000){
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val rounding = FpuRoundMode.elements.randomPick()
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val (a,b,c,f) = f32.sub(rounding).f32_2
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testBinaryOp(sub,a,b,c,f, rounding,"sub")
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}
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println("Add done")
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for(_ <- 0 until 100000){
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val rounding = FpuRoundMode.elements.randomPick()
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val (a,b,f) = f32.i2f(rounding).i32_f32
|
||||
testI2fExact(a,b,f, true, rounding)
|
||||
}
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.ui2f(rounding).i32_f32
|
||||
testI2fExact(a,b,f, false, rounding)
|
||||
}
|
||||
println("i2f done")
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.f2ui(rounding).f32_i32
|
||||
testF2iExact(a,b, f, false, rounding)
|
||||
}
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.f2i(rounding).f32_i32
|
||||
testF2iExact(a,b, f, true, rounding)
|
||||
|
|
@ -731,17 +736,63 @@ class FpuTest extends FunSuite{
|
|||
|
||||
println("f2i done")
|
||||
|
||||
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.mul(rounding).f32_2
|
||||
val (a,b,f) = f32.i2f(rounding).i32_f32
|
||||
testI2fExact(a,b,f, true, rounding)
|
||||
}
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.ui2f(rounding).i32_f32
|
||||
testI2fExact(a,b,f, false, rounding)
|
||||
}
|
||||
println("i2f done")
|
||||
|
||||
testBinaryOp(mul,1.469368E-39f, 7.9999995f, 1.17549435E-38f,3, FpuRoundMode.RUP,"mul")
|
||||
testBinaryOp(mul,1.1753509E-38f, 1.0001221f, 1.17549435E-38f ,1, FpuRoundMode.RUP,"mul")
|
||||
testBinaryOp(mul, 1.1754942E-38f, -1.0000001f, -1.17549435E-38f,1, FpuRoundMode.RNE,"mul")
|
||||
testBinaryOp(mul, 1.1754942E-38f, -1.0000001f, -1.17549435E-38f,1, FpuRoundMode.RDN,"mul")
|
||||
testBinaryOp(mul, 1.1754942E-38f, -1.0000001f, -1.17549435E-38f,1, FpuRoundMode.RMM,"mul")
|
||||
|
||||
testBinaryOp(mul, 1.1754945E-38f, 0.9999998f, 1.17549435E-38f, 3, FpuRoundMode.RUP, "mul")
|
||||
testBinaryOp(mul, 1.1754945E-38f, -0.9999998f, -1.17549435E-38f, 3, FpuRoundMode.RDN, "mul")
|
||||
testBinaryOp(mul, 1.1754946E-38f, 0.9999997f, 1.17549435E-38f, 3, FpuRoundMode.RUP, "mul")
|
||||
testBinaryOp(mul, 1.1754946E-38f, -0.9999997f, -1.17549435E-38f, 3, FpuRoundMode.RDN, "mul")
|
||||
testBinaryOp(mul, 1.1754949E-38f, 0.99999946f, 1.17549435E-38f, 3, FpuRoundMode.RUP, "mul")
|
||||
testBinaryOp(mul, 1.1754949E-38f, -0.99999946f, -1.17549435E-38f, 3, FpuRoundMode.RDN, "mul")
|
||||
testBinaryOp(mul, 1.1754955E-38f, 0.999999f, 1.17549435E-38f, 3, FpuRoundMode.RUP, "mul")
|
||||
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.mul(rounding).f32_f32
|
||||
testBinaryOp(mul,a,b,c,f, rounding,"mul")
|
||||
}
|
||||
|
||||
println("Mul done")
|
||||
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.add(rounding).f32_f32
|
||||
testBinaryOp(add,a,b,c,f, rounding,"add")
|
||||
}
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.sub(rounding).f32_f32
|
||||
testBinaryOp(sub,a,b,c,f, rounding,"sub")
|
||||
}
|
||||
|
||||
println("Add done")
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -823,7 +874,7 @@ class FpuTest extends FunSuite{
|
|||
|
||||
|
||||
testLoadStore(1.765f)
|
||||
testFmv_w_x(lang.Float.floatToIntBits(7.234f))
|
||||
testFmv_w_x(f2b(7.234f))
|
||||
testI2f(64, false)
|
||||
for(i <- iUnsigned) testI2f(i, false)
|
||||
for(i <- iSigned) testI2f(i, true)
|
||||
|
|
@ -874,7 +925,7 @@ class FpuTest extends FunSuite{
|
|||
|
||||
|
||||
testFmv_x_w(1.246f)
|
||||
testFmv_w_x(lang.Float.floatToIntBits(7.234f))
|
||||
testFmv_w_x(f2b(7.234f))
|
||||
|
||||
testMin(1.0f, 2.0f)
|
||||
testMin(1.5f, 2.0f)
|
||||
|
|
@ -989,7 +1040,7 @@ class FpuTest extends FunSuite{
|
|||
tests += (() =>{testSqrt(randomFloat().abs)})
|
||||
tests += (() =>{testCmp(randomFloat(), randomFloat())})
|
||||
tests += (() =>{testFmv_x_w(randomFloat())})
|
||||
tests += (() =>{testFmv_w_x(lang.Float.floatToIntBits(randomFloat()))})
|
||||
tests += (() =>{testFmv_w_x(f2b(randomFloat()))})
|
||||
tests += (() =>{testMin(randomFloat(), randomFloat())})
|
||||
tests += (() =>{testSgnj(randomFloat(), randomFloat())})
|
||||
|
||||
|
|
@ -1018,15 +1069,37 @@ object Clib {
|
|||
DoCmd.doCmd(cmd)
|
||||
val math = new FpuMath
|
||||
}
|
||||
|
||||
// cd /media/data/open/SaxonSoc/testFloatBuild/berkeley-softfloat-3/build/Linux-x86_64-GCC
|
||||
// make clean && SPECIALIZE_TYPE=RISCV make -j$(nproc) && cp softfloat.a /media/data/open/SaxonSoc/artyA7SmpUpdate/SaxonSoc/ext/VexRiscv/src/test/cpp/fpu/math
|
||||
object FpuCompileSo extends App{
|
||||
|
||||
val b2f = lang.Float.intBitsToFloat(_)
|
||||
for(e <- FpuRoundMode.elements) {
|
||||
println(e)
|
||||
for (i <- -2 until 50) println(i + " => " + Clib.math.addF32(b2f(0x7f000000), b2f(0x7f000000 + i), e.position))
|
||||
println("")
|
||||
}
|
||||
// val b2f = lang.Float.intBitsToFloat(_)
|
||||
// for(e <- FpuRoundMode.elements) {
|
||||
// println(e)
|
||||
// for (i <- -2 until 50) println(i + " => " + Clib.math.addF32(b2f(0x7f000000), b2f(0x7f000000 + i), e.position))
|
||||
// println("")
|
||||
// }
|
||||
//1 did not equal 3 Flag missmatch dut=1 ref=3 ## mul 0.9994812 -1.1754988E-38 -1.174889E-38 RMM
|
||||
// println(Clib.math.mulF32(0.9994812f, -1.1754988E-38f, FpuRoundMode.RMM.position))
|
||||
// miaou ffffffff 7fffffe0 7f
|
||||
// miaou 0 3ffffff0 70 = 0
|
||||
|
||||
|
||||
println(Clib.math.mulF32( 1.1753509E-38f, 1.0001221f, FpuRoundMode.RUP.position))
|
||||
println(Clib.math.mulF32( 1.1754945E-38f, 0.9999998f, FpuRoundMode.RUP.position))
|
||||
// testBinaryOp(mul, 1.1753509E-38f, 1.0001221f, 1.17549435E-38f ,1, FpuRoundMode.RUP,"mul")
|
||||
// testBinaryOp(mul, 1.1754945E-38f, 0.9999998f, 1.17549435E-38f, 3, FpuRoundMode.RUP, "mul")
|
||||
// miaou ffffffff 7fffffe0 7f
|
||||
// miaou 0 3ffffff0 70 = 0
|
||||
// miaou ffffffff 7fffff7e 7f
|
||||
// miaou 1 3fffffbf 3f = 1
|
||||
|
||||
// println(Clib.math.mulF32( 1.1753509E-38f, 1.0001221f, FpuRoundMode.RUP.position))
|
||||
// println(Clib.math.mulF32( 1.469368E-39f, 7.9999995f, FpuRoundMode.RUP.position))
|
||||
// println(Clib.math.mulF32( 1.40129846432e-45f, 7.9999995f, FpuRoundMode.RUP.position))
|
||||
// println(Clib.math.mulF32( 2.93873587706e-39f, 7.9999995f, FpuRoundMode.RUP.position))
|
||||
// println(Clib.math.mulF32( 1f, 7.9999995f, FpuRoundMode.RUP.position))
|
||||
|
||||
|
||||
// println(Clib.math.addF32(1.00000011921f, 4.0f, FpuRoundMode.RNE.position))
|
||||
// println(Clib.math.addF32(1.00000011921f, 4.0f, FpuRoundMode.RTZ.position))
|
||||
|
|
|
|||
Loading…
Reference in New Issue