fpu test wip
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3710fd3492
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@ -8,6 +8,7 @@ import org.apache.commons.io.FileUtils
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import org.scalatest.FunSuite
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import spinal.core.SpinalEnumElement
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import spinal.core.sim._
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import spinal.core._
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import spinal.lib.DoCmd
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import spinal.lib.experimental.math.Floating
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import spinal.lib.sim._
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@ -38,7 +39,9 @@ class FpuTest extends FunSuite{
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val config = SimConfig
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// config.withFstWave
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config.compile(new FpuCore(portCount, p)).doSim(seed = 42){ dut =>
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config.compile(new FpuCore(portCount, p){
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for(i <- 0 until portCount) out(Bits(5 bits)).setName(s"flagAcc$i") := io.port(i).completion.flag.asBits
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}).doSim(seed = 42){ dut =>
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dut.clockDomain.forkStimulus(10)
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dut.clockDomain.forkSimSpeedPrinter(5.0)
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@ -92,6 +95,21 @@ class FpuTest extends FunSuite{
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val commitQueue = mutable.Queue[FpuCommit => Unit]()
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val rspQueue = mutable.Queue[FpuRsp => Unit]()
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var pending = 0
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var flagAccumulator = 0
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def cmdAdd(body : FpuCmd => Unit): Unit ={
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pending += 1
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cmdQueue += body
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}
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val flagAggregated = dut.reflectBaseType(s"flagAcc$id").asInstanceOf[Bits]
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dut.clockDomain.onSamplings{
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val c = dut.io.port(id).completion
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pending -= c.count.toInt
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flagAccumulator |= flagAggregated.toInt
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}
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StreamDriver(dut.io.port(id).cmd ,dut.clockDomain){payload =>
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if(cmdQueue.isEmpty) false else {
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cmdQueue.dequeue().apply(payload)
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@ -114,9 +132,11 @@ class FpuTest extends FunSuite{
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}
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}
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def loadRaw(rd : Int, value : BigInt): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.LOAD
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cmd.rs1.randomize()
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cmd.rs2.randomize()
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@ -136,7 +156,7 @@ class FpuTest extends FunSuite{
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}
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def storeRaw(rs : Int)(body : FpuRsp => Unit): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.STORE
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cmd.rs1 #= rs
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cmd.rs2.randomize()
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@ -154,7 +174,7 @@ class FpuTest extends FunSuite{
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}
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def fpuF2f(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int, opcode : FpuOpcode.E, arg : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= opcode
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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@ -170,7 +190,7 @@ class FpuTest extends FunSuite{
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}
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def fpuF2i(rs1 : Int, rs2 : Int, opcode : FpuOpcode.E, arg : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE)(body : FpuRsp => Unit): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= opcode
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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@ -217,7 +237,7 @@ class FpuTest extends FunSuite{
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}
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def i2f(rd : Int, value : Int, signed : Boolean, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.I2F
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cmd.rs1.randomize()
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cmd.rs2.randomize()
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@ -234,7 +254,7 @@ class FpuTest extends FunSuite{
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}
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def fmv_x_w(rs1 : Int)(body : FpuRsp => Unit): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.FMV_X_W
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cmd.rs1 #= rs1
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cmd.rs2.randomize()
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@ -246,7 +266,7 @@ class FpuTest extends FunSuite{
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}
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def fmv_w_x(rd : Int, value : Int): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.FMV_W_X
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cmd.rs1.randomize()
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cmd.rs2.randomize()
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@ -262,7 +282,7 @@ class FpuTest extends FunSuite{
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}
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def min(rd : Int, rs1 : Int, rs2 : Int): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.MIN_MAX
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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@ -278,7 +298,7 @@ class FpuTest extends FunSuite{
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def sgnj(rd : Int, rs1 : Int, rs2 : Int): Unit ={
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cmdQueue += {cmd =>
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cmdAdd {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.SGNJ
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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