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#60 Add sim error message on RVC instruction without RVC capabilities

This commit is contained in:
Charles Papon 2019-04-13 10:44:06 +02:00
parent 5d1ec604b2
commit 61d25e931e
1 changed files with 1 additions and 0 deletions
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src/test/cpp/regression/main.cpp
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@ -958,6 +958,7 @@ public:
} }
} else { } else {
#ifndef COMPRESSED #ifndef COMPRESSED
cout << "ERROR : RiscvGolden got a RVC instruction while the CPU isn't RVC ready" << endl;
ilegalInstruction(); return; ilegalInstruction(); return;
#endif #endif
switch((iBits(0, 2) << 3) + iBits(13, 3)){ switch((iBits(0, 2) << 3) + iBits(13, 3)){