#60 Add sim error message on RVC instruction without RVC capabilities

2019-04-13 10:44:06 +02:00 · 2019-04-13 10:44:06 +02:00 · 61d25e931e
parent 5d1ec604b2
commit 61d25e931e
1 changed files with 1 additions and 0 deletions
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@ -958,6 +958,7 @@ public:
 			}
 		} else {
 			#ifndef COMPRESSED
+			cout << "ERROR : RiscvGolden got a RVC instruction while the CPU isn't RVC ready" << endl;
 	        ilegalInstruction(); return;
 			#endif
 			switch((iBits(0, 2) << 3) + iBits(13, 3)){