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smp cluster add more profiling

This commit is contained in:
Dolu1990 2020-05-11 10:35:24 +02:00
parent b592b0bff8
commit 63511b19a2
1 changed files with 14 additions and 2 deletions
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16
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -533,6 +533,9 @@ object VexRiscvSmpClusterOpenSbi extends App{
var iMemReadBytes, dMemReadBytes, dMemWriteBytes, iMemSequencial,iMemRequests = 0l var iMemReadBytes, dMemReadBytes, dMemWriteBytes, iMemSequencial,iMemRequests = 0l
var reportTimer = 0 var reportTimer = 0
var reportCycle = 0 var reportCycle = 0
var dMemWrites, dMemWritesCached = 0l
var dMemWriteCacheAddress = 0l
val dMemWriteCacheMask = ~((1 << log2Up(128/8))-1)
import java.io._ import java.io._
val csv = new PrintWriter(new File("bench.csv" )) val csv = new PrintWriter(new File("bench.csv" ))
@ -540,7 +543,6 @@ object VexRiscvSmpClusterOpenSbi extends App{
var sequencialPrediction = 0l var sequencialPrediction = 0l
val cache = dut.cpus(i).core.children.find(_.isInstanceOf[InstructionCache]).head.asInstanceOf[InstructionCache].io.cpu.decode val cache = dut.cpus(i).core.children.find(_.isInstanceOf[InstructionCache]).head.asInstanceOf[InstructionCache].io.cpu.decode
}) })
csv.write(s"reportCycle,iMemReadBytes,dMemReadBytes,dMemWriteBytes,miaou,asd\n")
dut.clockDomain.onSamplings{ dut.clockDomain.onSamplings{
for(i <- 0 until cpuCount; iMem = dut.io.iMems(i); ctx = iMemCtx(i)){ for(i <- 0 until cpuCount; iMem = dut.io.iMems(i); ctx = iMemCtx(i)){
// if(iMem.cmd.valid.toBoolean && iMem.cmd.ready.toBoolean){ // if(iMem.cmd.valid.toBoolean && iMem.cmd.ready.toBoolean){
@ -568,6 +570,13 @@ object VexRiscvSmpClusterOpenSbi extends App{
if(dut.io.dMem.cmd.valid.toBoolean && dut.io.dMem.cmd.ready.toBoolean){ if(dut.io.dMem.cmd.valid.toBoolean && dut.io.dMem.cmd.ready.toBoolean){
if(dut.io.dMem.cmd.opcode.toInt == Bmb.Cmd.Opcode.WRITE){ if(dut.io.dMem.cmd.opcode.toInt == Bmb.Cmd.Opcode.WRITE){
dMemWriteBytes += dut.io.dMem.cmd.length.toInt+1 dMemWriteBytes += dut.io.dMem.cmd.length.toInt+1
val address = dut.io.dMem.cmd.address.toLong
dMemWrites += 1
if((address & dMemWriteCacheMask) == (dMemWriteCacheAddress & dMemWriteCacheMask)){
dMemWritesCached += 1
} else {
dMemWriteCacheAddress = address
}
}else { }else {
dMemReadBytes += dut.io.dMem.cmd.length.toInt+1 dMemReadBytes += dut.io.dMem.cmd.length.toInt+1
} }
@ -578,7 +587,8 @@ object VexRiscvSmpClusterOpenSbi extends App{
reportTimer = 0 reportTimer = 0
// println(f"\n** c=${reportCycle} ir=${iMemReadBytes*1e-6}%5.2f dr=${dMemReadBytes*1e-6}%5.2f dw=${dMemWriteBytes*1e-6}%5.2f **\n") // println(f"\n** c=${reportCycle} ir=${iMemReadBytes*1e-6}%5.2f dr=${dMemReadBytes*1e-6}%5.2f dw=${dMemWriteBytes*1e-6}%5.2f **\n")
csv.write(s"$reportCycle,$iMemReadBytes,$dMemReadBytes,$dMemWriteBytes,$iMemRequests,$iMemSequencial\n")
csv.write(s"$reportCycle,$iMemReadBytes,$dMemReadBytes,$dMemWriteBytes,$iMemRequests,$iMemSequencial,$dMemWrites,$dMemWritesCached\n")
csv.flush() csv.flush()
reportCycle = 0 reportCycle = 0
iMemReadBytes = 0 iMemReadBytes = 0
@ -586,6 +596,8 @@ object VexRiscvSmpClusterOpenSbi extends App{
dMemWriteBytes = 0 dMemWriteBytes = 0
iMemRequests = 0 iMemRequests = 0
iMemSequencial = 0 iMemSequencial = 0
dMemWrites = 0
dMemWritesCached = 0
} }
} }