Add regression TRACE_SPORADIC, LINUX_SOC_SMP
regression golden model now properly sync dut exceptions
This commit is contained in:
Charles Papon
parent
0a159f06b2
commit
b592b0bff8
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@ -28,6 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
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// make clean all SEED=42 MMU=no STOP_ON_ERROR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes SUPERVISOR=yes REDO=1 DHRYSTONE=yes LRSC=yes AMO=yes LINUX_REGRESSION=yes TRACE=yes TRACE_START=1000000000 FLOW_INFO=ye IBUS_DATA_WIDTH=128 DBUS_DATA_WIDTH=128
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//make clean all SEED=42 MMU=no STOP_ON_ERROR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes SUPERVISOR=yes REDO=1 DHRYSTONE=yes LRSC=yes AMO=yes TRACE=yes TRACE_START=1000000000 FLOW_INFO=ye IBUS_DATA_WIDTH=128 DBUS_DATA_WIDTH=128 LINUX_SOC_SMP=yes VMLINUX=../../../../../buildroot/output/images/Image RAMDISK=../../../../../buildroot/output/images/rootfs.cpio DTB=../../../../../buildroot/output/images/dtb EMULATOR=../../../../../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin
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object TestsWorkspace {
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def main(args: Array[String]) {
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def configFull = {
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@ -156,7 +157,7 @@ object TestsWorkspace {
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divUnrollFactor = 1
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),
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// new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = false)),
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new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = false, misaExtensionsInit = Riscv.misaToInt("imas"))),
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// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
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// CsrPluginConfig(
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// catchIllegalAccess = false,
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@ -8,6 +8,7 @@ import vexriscv.plugin.IntAluPlugin.{ALU_BITWISE_CTRL, ALU_CTRL, AluBitwiseCtrlE
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable
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import spinal.core.sim._
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/**
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* Created by spinalvm on 21.03.17.
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@ -874,7 +875,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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interruptJump := interrupt.valid && pipelineLiberator.done && allowInterrupts
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if(pipelinedInterrupt) interrupt.valid clearWhen(interruptJump) //avoid double fireing
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val hadException = RegNext(exception) init(False)
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val hadException = RegNext(exception) init(False) addTag(Verilator.public)
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pipelineLiberator.done.clearWhen(hadException)
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@ -390,7 +390,7 @@ public:
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mcause.raw = 0;
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mbadaddr = 0;
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mepc = 0;
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misa = 0; //TODO
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misa = 0x40041101; //TODO
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status.raw = 0;
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status.mpp = 3;
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status.spp = 1;
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@ -401,6 +401,7 @@ public:
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ipSoft = 0;
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ipInput = 0;
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stepCounter = 0;
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sbadaddr = 42;
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lrscReserved = false;
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}
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@ -513,7 +514,7 @@ public:
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pcWrite(xtvec.base << 2);
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if(interrupt) livenessInterrupt = 0;
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if(!interrupt) step(); //As VexRiscv instruction which trap do not reach writeback stage fire
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// if(!interrupt) step(); //As VexRiscv instruction which trap do not reach writeback stage fire
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}
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uint32_t currentInstruction;
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@ -540,6 +541,7 @@ public:
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case MISA: *value = misa; break;
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case MEDELEG: *value = medeleg; break;
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case MIDELEG: *value = mideleg; break;
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case MHARTID: *value = 0; break;
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case SSTATUS: *value = status.raw & 0xC0133; break;
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case SIP: *value = getIp().raw & 0x333; break;
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@ -578,7 +580,7 @@ public:
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case MEPC: mepc = value; break;
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case MSCRATCH: mscratch = value; break;
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case MISA: misa = value; break;
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case MEDELEG: medeleg = value; break;
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case MEDELEG: medeleg = value & (~0x8); break;
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case MIDELEG: mideleg = value; break;
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case SSTATUS: maskedWrite(status.raw, value,0xC0133); break;
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@ -1259,7 +1261,7 @@ public:
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top = new VVexRiscv;
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#ifdef TRACE_ACCESS
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regTraces.open (name + ".regTrace");
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memTraces.open (name + ".memTrace");hh
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memTraces.open (name + ".memTrace");
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#endif
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logTraces.open (name + ".logTrace");
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debugLog.open (name + ".debugTrace");
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@ -1342,7 +1344,7 @@ public:
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#endif
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) <<
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#endif
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" : WRITE mem" << (1 << size) << "[" << addr << "] = " << *data << endl;
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" : WRITE mem" << hex << (1 << size) << "[" << addr << "] = " << *data << dec << endl;
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for(uint32_t b = 0;b < (1 << size);b++){
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uint32_t offset = (addr+b)&0x3;
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if((mask >> offset) & 1 == 1)
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@ -1356,6 +1358,7 @@ public:
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*data &= ~(0xFF << (offset*8));
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*data |= mem[addr + b] << (offset*8);
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}
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/*
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memTraces <<
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#ifdef TRACE_WITH_TIME
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(currentTime
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@ -1364,7 +1367,7 @@ public:
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#endif
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) <<
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#endif
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" : READ mem" << (1 << size) << "[" << addr << "] = " << *data << endl;
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" : READ mem" << (1 << size) << "[" << addr << "] = " << *data << endl;*/
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}
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}
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@ -1430,6 +1433,9 @@ public:
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#ifdef TRACE
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if(i == TRACE_START && i != 0) cout << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "START TRACE" << endl;
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if(i >= TRACE_START) tfp->dump(i);
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#ifdef TRACE_SPORADIC
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else if(i % 1000000 < 100) tfp->dump(i);
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#endif
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#endif
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}
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@ -1624,6 +1630,14 @@ public:
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}
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}
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#ifdef CSR
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if(top->VexRiscv->CsrPlugin_hadException){
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if(riscvRefEnable) {
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riscvRef.step();
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}
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}
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#endif
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for(SimElement* simElement : simElements) simElement->preCycle();
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dump(i + 1);
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@ -3451,7 +3465,6 @@ public:
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}
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};
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class LinuxRegression: public LinuxSoc{
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public:
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string pendingLine = "";
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@ -3484,6 +3497,82 @@ public:
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#endif
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#ifdef LINUX_SOC_SMP
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class LinuxSocSmp : public Workspace{
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public:
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queue <char> customCin;
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void pushCin(string m){
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for(char& c : m) {
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customCin.push(c);
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}
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}
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LinuxSocSmp(string name) : Workspace(name) {
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#ifdef WITH_USER_IO
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stdinNonBuffered();
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captureCtrlC();
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#endif
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stdoutNonBuffered();
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}
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virtual ~LinuxSocSmp(){
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#ifdef WITH_USER_IO
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stdinRestore();
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#endif
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}
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virtual bool isDBusCheckedRegion(uint32_t address){ return true;}
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virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xF0000000;}
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virtual bool isMmuRegion(uint32_t addr) { return true; }
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virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
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if(isPerifRegion(addr)) switch(addr){
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//TODO Emulate peripherals here
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case 0xF0010000: if(wr && *data != 0) fail(); else *data = 0; break;
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case 0xF001BFF8: if(wr) fail(); else *data = mTime; break;
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case 0xF001BFFC: if(wr) fail(); else *data = mTime >> 32; break;
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case 0xF0014000: if(wr) mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | *data; else fail(); break;
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case 0xF0014004: if(wr) mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); else fail(); break;
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case 0xF0000000:
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if(wr){
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char c = (char)*data;
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cout << c;
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logTraces << c;
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logTraces.flush();
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onStdout(c);
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}
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case 0xF0000004:
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if(!wr){
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#ifdef WITH_USER_IO
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if(stdinNonEmpty()){
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char c;
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read(0, &c, 1);
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*data = c;
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} else
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#endif
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if(!customCin.empty()){
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*data = customCin.front();
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customCin.pop();
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} else {
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*data = -1;
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}
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}
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break;
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default: cout << "Unmapped peripheral access : addr=0x" << hex << addr << " wr=" << wr << " mask=0x" << mask << " data=0x" << data << dec << endl; fail(); break;
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}
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Workspace::dBusAccess(addr,wr,size,mask,data,error);
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}
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virtual void onStdout(char c){
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}
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};
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#endif
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string riscvTestMain[] = {
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//"rv32ui-p-simple",
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"rv32ui-p-lui",
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@ -3840,6 +3929,27 @@ int main(int argc, char **argv, char **env) {
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#endif
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#ifdef LINUX_SOC_SMP
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{
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LinuxSocSmp soc("linuxSmp");
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#ifndef DEBUG_PLUGIN_EXTERNAL
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soc.withRiscvRef();
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soc.loadBin(EMULATOR, 0x80000000);
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soc.loadBin(VMLINUX, 0xC0000000);
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soc.loadBin(DTB, 0xC4000000);
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soc.loadBin(RAMDISK, 0xC2000000);
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#endif
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//soc.setIStall(true);
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//soc.setDStall(true);
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soc.bootAt(0x80000000);
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soc.run(0);
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// soc.run((496300000l + 2000000) / 2);
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// soc.run(438700000l/2);
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return -1;
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}
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#endif
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@ -9,6 +9,7 @@ DBUS_DATA_WIDTH?=32
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TRACE?=no
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TRACE_ACCESS?=no
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TRACE_START=0
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TRACE_SPORADIC?=no
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ISA_TEST?=yes
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MUL?=yes
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DIV?=yes
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@ -84,6 +85,15 @@ ifeq ($(LINUX_SOC),yes)
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ADDCFLAGS += -CFLAGS -DEMULATOR='\"$(EMULATOR)\"'
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endif
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ifeq ($(LINUX_SOC_SMP),yes)
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ADDCFLAGS += -CFLAGS -DLINUX_SOC_SMP
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ADDCFLAGS += -CFLAGS -DVMLINUX='\"$(VMLINUX)\"'
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ADDCFLAGS += -CFLAGS -DDTB='\"$(DTB)\"'
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ADDCFLAGS += -CFLAGS -DRAMDISK='\"$(RAMDISK)\"'
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ADDCFLAGS += -CFLAGS -DEMULATOR='\"$(EMULATOR)\"'
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endif
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ARCH_LINUX=rv32i
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ifeq ($(MUL),yes)
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ifeq ($(DIV),yes)
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@ -187,6 +197,12 @@ ifeq ($(TRACE),yes)
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ADDCFLAGS += -CFLAGS -DTRACE
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endif
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ifeq ($(TRACE_SPORADIC),yes)
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ADDCFLAGS += -CFLAGS -DTRACE_SPORADIC
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endif
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ifeq ($(CSR),yes)
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ADDCFLAGS += -CFLAGS -DCSR
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endif
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