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VexRiscvAxi4Linux now integrate Plic and Clint

This commit is contained in:
Dolu1990 2022-10-26 10:15:21 +02:00
parent 220af95043
commit 63dd787bce
1 changed files with 37 additions and 27 deletions
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64
src/main/scala/vexriscv/demo/VexRiscvAxi4Linux.scala → src/main/scala/vexriscv/demo/VexRiscvAxi4LinuxPlicClint.scala
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@ -2,15 +2,18 @@ package vexriscv.demo
import spinal.core._ import spinal.core._
import spinal.lib._ import spinal.lib._
import spinal.lib.bus.amba4.axi.Axi4ReadOnly import spinal.lib.bus.amba4.axi.{Axi4ReadOnly, Axi4SpecRenamer}
import spinal.lib.bus.amba4.axilite.AxiLite4SpecRenamer
import spinal.lib.com.jtag.Jtag import spinal.lib.com.jtag.Jtag
import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag} import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
import spinal.lib.misc.AxiLite4Clint
import spinal.lib.misc.plic.AxiLite4Plic
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.plugin._ import vexriscv.plugin._
import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin} import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
object VexRiscvAxi4Linux{ object VexRiscvAxi4LinuxPlicClint{
def main(args: Array[String]) { def main(args: Array[String]) {
val report = SpinalVerilog{ val report = SpinalVerilog{
@ -99,36 +102,42 @@ object VexRiscvAxi4Linux{
) )
//CPU instanciation //CPU instanciation
val cpu = new VexRiscv(cpuConfig) val cpu = new VexRiscv(cpuConfig){
val clintCtrl = new AxiLite4Clint(1, bufferTime = false)
val plicCtrl = new AxiLite4Plic(
sourceCount = 31,
targetCount = 2
)
val clint = clintCtrl.io.bus.toIo()
val plic = plicCtrl.io.bus.toIo()
val plicInterrupts = in Bits(32 bits)
plicCtrl.io.sources := plicInterrupts >> 1
AxiLite4SpecRenamer(clint)
AxiLite4SpecRenamer(plic)
}
//CPU modifications to be an Avalon one //CPU modifications to be an Avalon one
cpu.setDefinitionName("VexRiscvAxi4") cpu.setDefinitionName("VexRiscvAxi4LinuxPlicClint")
cpu.rework { cpu.rework {
var iBus : Axi4ReadOnly = null
for (plugin <- cpuConfig.plugins) plugin match { for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => {
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: IBusCachedPlugin => { case plugin: IBusCachedPlugin => {
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig()) Axi4SpecRenamer(
.setName("iBusAxi") master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .setName("iBusAxi")
} .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
case plugin: DBusSimplePlugin => { )
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DBusCachedPlugin => { case plugin: DBusCachedPlugin => {
plugin.dBus.setAsDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi") Axi4SpecRenamer(
.addTag(ClockDomainTag(ClockDomain.current)) master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current))
)
} }
case plugin: DebugPlugin => plugin.debugClockDomain { case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess() plugin.io.bus.setAsDirectionLess()
@ -143,10 +152,11 @@ object VexRiscvAxi4Linux{
} }
for (plugin <- cpuConfig.plugins) plugin match { for (plugin <- cpuConfig.plugins) plugin match {
case plugin: CsrPlugin => { case plugin: CsrPlugin => {
plugin.externalInterrupt plugin.timerInterrupt setAsDirectionLess() := cpu.clintCtrl.io.timerInterrupt(0)
.addTag(InterruptReceiverTag(iBus, ClockDomain.current)) plugin.softwareInterrupt setAsDirectionLess() := cpu.clintCtrl.io.softwareInterrupt(0)
plugin.timerInterrupt plugin.externalInterrupt setAsDirectionLess() := cpu.plicCtrl.io.targets(0)
.addTag(InterruptReceiverTag(iBus, ClockDomain.current)) plugin.externalInterruptS setAsDirectionLess() := cpu.plicCtrl.io.targets(1)
plugin.utime setAsDirectionLess() := cpu.clintCtrl.io.time
} }
case _ => case _ =>
} }