Add VexRiscvAxi4Linux (untested, but generate a netlist)
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Dolu1990
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959e48a353
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220af95043
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package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.Axi4ReadOnly
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
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object VexRiscvAxi4Linux{
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def main(args: Array[String]) {
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val report = SpinalVerilog{
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//CPU configuration
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val cpuConfig = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusCachedPlugin(
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prediction = STATIC,
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine = 64,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = true,
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twoCycleCache = true
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4,
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latency = 1,
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earlyRequireMmuLockup = true,
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earlyCacheHits = true
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)
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 64,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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withLrSc = true,
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withAmo = true
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4,
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latency = 1,
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earlyRequireMmuLockup = true,
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earlyCacheHits = true
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)
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),
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new MmuPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrelShifterPlugin,
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new MulPlugin,
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new DivPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true
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),
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new CsrPlugin(CsrPluginConfig.openSbi(mhartid = 0, misa = Riscv.misaToInt(s"ima")).copy(utimeAccess = CsrAccess.READ_ONLY)),
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new YamlPlugin("cpu0.yaml")
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)
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)
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//CPU instanciation
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val cpu = new VexRiscv(cpuConfig)
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//CPU modifications to be an Avalon one
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cpu.setDefinitionName("VexRiscvAxi4")
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cpu.rework {
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var iBus : Axi4ReadOnly = null
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for (plugin <- cpuConfig.plugins) plugin match {
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case plugin: IBusSimplePlugin => {
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plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
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iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
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.setName("iBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
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}
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case plugin: IBusCachedPlugin => {
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plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
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iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
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.setName("iBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
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}
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case plugin: DBusSimplePlugin => {
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plugin.dBus.setAsDirectionLess()
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master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
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.setName("dBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current))
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}
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case plugin: DBusCachedPlugin => {
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plugin.dBus.setAsDirectionLess()
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master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
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.setName("dBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current))
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}
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case plugin: DebugPlugin => plugin.debugClockDomain {
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plugin.io.bus.setAsDirectionLess()
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val jtag = slave(new Jtag())
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.setName("jtag")
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jtag <> plugin.io.bus.fromJtag()
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plugin.io.resetOut
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.addTag(ResetEmitterTag(plugin.debugClockDomain))
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.parent = null //Avoid the io bundle to be interpreted as a QSys conduit
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}
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case _ =>
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}
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for (plugin <- cpuConfig.plugins) plugin match {
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case plugin: CsrPlugin => {
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plugin.externalInterrupt
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.addTag(InterruptReceiverTag(iBus, ClockDomain.current))
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plugin.timerInterrupt
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.addTag(InterruptReceiverTag(iBus, ClockDomain.current))
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}
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case _ =>
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}
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}
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cpu
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}
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}
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}
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