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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl

This commit is contained in:
Dolu1990 2018-03-15 18:56:25 +01:00
parent 63c1b738ff
commit 64022557bf
1 changed files with 6 additions and 2 deletions
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8
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
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@ -9,12 +9,16 @@ import scala.collection.mutable.ArrayBuffer
object KeepAttribute{
object syn_keep extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
object syn_keep_verilog extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
override def isLanguageReady(language: Language) : Boolean = language == Language.VERILOG || language == Language.SYSTEM_VERILOG
}
object syn_keep_vhdl extends AttributeFlag("syn_keep"){
override def isLanguageReady(language: Language) : Boolean = language == Language.VHDL
}
object keep extends AttributeFlag("keep")
def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep)
def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep_verilog).addAttribute(syn_keep_vhdl)
}
class PcManagerSimplePlugin(resetVector : BigInt,
relaxedPcCalculation : Boolean = false,