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VexRiscv
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wishbone => word address, not byte address

This commit is contained in:
Dolu1990 2018-04-19 11:22:06 +02:00
parent 455607b6b4
commit 6598e82920
3 changed files with 7 additions and 9 deletions
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4
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -48,7 +48,7 @@ case class DataCacheConfig( cacheSize : Int,
) )
def getWishboneConfig() = WishboneConfig( def getWishboneConfig() = WishboneConfig(
addressWidth = 32, addressWidth = 30,
dataWidth = 32, dataWidth = 32,
selWidth = 4, selWidth = 4,
useSTALL = false, useSTALL = false,
@ -326,7 +326,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
} }
bus.ADR := cmdBridge.address bus.ADR := cmdBridge.address >> 2
bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000") bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
bus.BTE := "00" bus.BTE := "00"
bus.SEL := cmdBridge.wr ? cmdBridge.mask | "1111" bus.SEL := cmdBridge.wr ? cmdBridge.mask | "1111"

4
src/main/scala/vexriscv/ip/InstructionCache.scala
View File

@ -44,7 +44,7 @@ case class InstructionCacheConfig( cacheSize : Int,
) )
def getWishboneConfig() = WishboneConfig( def getWishboneConfig() = WishboneConfig(
addressWidth = 32, addressWidth = 30,
dataWidth = 32, dataWidth = 32,
selWidth = 4, selWidth = 4,
useSTALL = false, useSTALL = false,
@ -172,7 +172,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
val pending = counter =/= 0 val pending = counter =/= 0
val lastCycle = counter === counter.maxValue val lastCycle = counter === counter.maxValue
bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter @@ "00" bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter
bus.CTI := lastCycle ? B"111" | B"010" bus.CTI := lastCycle ? B"111" | B"010"
bus.BTE := "00" bus.BTE := "00"
bus.SEL := "1111" bus.SEL := "1111"

8
src/test/cpp/regression/main.cpp
View File

@ -710,12 +710,11 @@ public:
virtual void preCycle(){ virtual void preCycle(){
top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32); top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32);
if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) { if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) {
assertEq(top->iBusWishbone_ADR & 3,0);
if(top->iBusWishbone_WE){ if(top->iBusWishbone_WE){
} else { } else {
bool error; bool error;
ws->iBusAccess(top->iBusWishbone_ADR,&top->iBusWishbone_DAT_MISO,&error); ws->iBusAccess(top->iBusWishbone_ADR << 2,&top->iBusWishbone_DAT_MISO,&error);
top->iBusWishbone_ERR = error; top->iBusWishbone_ERR = error;
} }
} }
@ -848,13 +847,12 @@ public:
virtual void preCycle(){ virtual void preCycle(){
top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32); top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32);
if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) { if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) {
assertEq(top->dBusWishbone_ADR & 3,0);
if(top->dBusWishbone_WE){ if(top->dBusWishbone_WE){
bool dummy; bool dummy;
ws->dBusAccess(top->dBusWishbone_ADR,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy); ws->dBusAccess(top->dBusWishbone_ADR << 2 ,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy);
} else { } else {
bool error; bool error;
ws->dBusAccess(top->dBusWishbone_ADR,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error); ws->dBusAccess(top->dBusWishbone_ADR << 2,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error);
top->dBusWishbone_ERR = error; top->dBusWishbone_ERR = error;
} }
} }