Fix wishbone bridges with datawidth > 32
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@ -334,7 +334,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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val cmdBridge = Stream (DataCacheMemCmd(p))
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val isBurst = cmdBridge.isBurst
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cmdBridge.valid := cmd.valid
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cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits)))
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cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto addressShift) @@ U(0, addressShift bits)))
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cmdBridge.wr := cmd.wr
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cmdBridge.mask := cmd.mask
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cmdBridge.data := cmd.data
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@ -351,7 +351,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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}
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bus.ADR := cmdBridge.address >> 2
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bus.ADR := cmdBridge.address >> addressShift
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bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
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bus.BTE := B"00"
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bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)
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