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VexRiscv
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Fix wishbone bridges with datawidth > 32

This commit is contained in:
Dolu1990 2021-09-17 09:43:30 +02:00
parent c1481ae244
commit 65cda95176
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/ip/DataCache.scala
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@ -334,7 +334,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
val cmdBridge = Stream (DataCacheMemCmd(p)) val cmdBridge = Stream (DataCacheMemCmd(p))
val isBurst = cmdBridge.isBurst val isBurst = cmdBridge.isBurst
cmdBridge.valid := cmd.valid cmdBridge.valid := cmd.valid
cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits))) cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto addressShift) @@ U(0, addressShift bits)))
cmdBridge.wr := cmd.wr cmdBridge.wr := cmd.wr
cmdBridge.mask := cmd.mask cmdBridge.mask := cmd.mask
cmdBridge.data := cmd.data cmdBridge.data := cmd.data
@ -351,7 +351,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
} }
bus.ADR := cmdBridge.address >> 2 bus.ADR := cmdBridge.address >> addressShift
bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000") bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
bus.BTE := B"00" bus.BTE := B"00"
bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1) bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)