Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)
Add MuraxConfig.fast
This commit is contained in:
Charles Papon
parent
9f65a21f3e
commit
671aa5050e
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@ -12,6 +12,8 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
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import vexriscv.plugin._
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import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
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import scala.collection.mutable.ArrayBuffer
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/**
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* Created by PIC32F_USER on 28/07/2017.
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*
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@ -29,31 +31,105 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
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case class MuraxConfig(coreFrequency : HertzNumber,
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onChipRamSize : BigInt,
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onChipRamHexFile : String,
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bypassExecute : Boolean,
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bypassMemory: Boolean,
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bypassWriteBack: Boolean,
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bypassWriteBackBuffer : Boolean,
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pipelineDBus : Boolean,
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pipelineMainBus : Boolean,
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pipelineApbBridge : Boolean){
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onChipRamSize : BigInt,
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onChipRamHexFile : String,
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pipelineDBus : Boolean,
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pipelineMainBus : Boolean,
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pipelineApbBridge : Boolean,
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gpioWidth : Int,
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uartCtrlConfig : UartCtrlMemoryMappedConfig,
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cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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}
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object MuraxConfig{
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def default = MuraxConfig(
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coreFrequency = 12 MHz,
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onChipRamSize = 8 kB,
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onChipRamHexFile = null,
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pipelineDBus = true,
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pipelineMainBus = false,
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pipelineApbBridge = true
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coreFrequency = 12 MHz,
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onChipRamSize = 8 kB,
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onChipRamHexFile = null,
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pipelineDBus = true,
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pipelineMainBus = false,
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pipelineApbBridge = true,
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gpioWidth = 32,
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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new PcManagerSimplePlugin(
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resetVector = 0x00000000l,
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relaxedPcCalculation = true
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),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false,
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earlyInjection = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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),
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uartCtrlConfig = UartCtrlMemoryMappedConfig(
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uartCtrlConfig = UartCtrlGenerics(
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dataWidthMax = 8,
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clockDividerWidth = 20,
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preSamplingSize = 1,
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samplingSize = 3,
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postSamplingSize = 1
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),
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initConfig = UartCtrlInitConfig(
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baudrate = 115200,
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dataLength = 7, //7 => 8 bits
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parity = UartParityType.NONE,
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stop = UartStopType.ONE
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),
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busCanWriteClockDividerConfig = false,
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busCanWriteFrameConfig = false,
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txFifoDepth = 16,
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rxFifoDepth = 16
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)
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)
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def fast = {
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val config = default
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//Replace HazardSimplePlugin to get datapath bypass
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config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true
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)
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config
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}
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}
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case class SimpleBusCmd() extends Bundle{
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@ -139,51 +215,7 @@ case class Murax(config : MuraxConfig) extends Component{
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//Instanciate the CPU
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val cpu = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(
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resetVector = 0x00000000l,
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relaxedPcCalculation = true
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),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false,
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earlyInjection = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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),
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new LightShifterPlugin,
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new DebugPlugin(debugClockDomain),
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new HazardSimplePlugin(
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bypassExecute = bypassExecute,
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bypassMemory = bypassMemory,
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bypassWriteBack = bypassWriteBack,
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bypassWriteBackBuffer = bypassWriteBackBuffer,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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plugins = cpuPlugins += new DebugPlugin(debugClockDomain)
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)
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)
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@ -379,30 +411,10 @@ case class Murax(config : MuraxConfig) extends Component{
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}
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val gpioACtrl = Apb3Gpio(
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gpioWidth = 32
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gpioWidth = gpioWidth
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)
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io.gpioA <> gpioACtrl.io.gpio
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val uartCtrlConfig = UartCtrlMemoryMappedConfig(
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uartCtrlConfig = UartCtrlGenerics(
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dataWidthMax = 8,
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clockDividerWidth = 20,
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preSamplingSize = 1,
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samplingSize = 3,
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postSamplingSize = 1
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),
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initConfig = UartCtrlInitConfig(
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baudrate = 115200,
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dataLength = 7, //7 => 8 bits
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parity = UartParityType.NONE,
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stop = UartStopType.ONE
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),
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busCanWriteClockDividerConfig = false,
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busCanWriteFrameConfig = false,
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txFifoDepth = 16,
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rxFifoDepth = 16
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)
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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uartCtrl.io.uart <> io.uart
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externalInterrupt setWhen(uartCtrl.io.interrupt)
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@ -454,6 +466,7 @@ case class Murax(config : MuraxConfig) extends Component{
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object Murax{
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.default))
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// SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) //dhrystone config (more ram)
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}
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}
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@ -107,12 +107,7 @@ object MuraxSynthesisBench {
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override def getName(): String = "MuraxFast"
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override def getRtlPath(): String = "MuraxFast.v"
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SpinalVerilog({
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val murax = new Murax(MuraxConfig.default.copy(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true
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)).setDefinitionName(getRtlPath().split("\\.").head)
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val murax = new Murax(MuraxConfig.fast).setDefinitionName(getRtlPath().split("\\.").head)
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murax.io.mainClk.setName("clk")
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murax
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})
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