Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)

Add MuraxConfig.fast

src/main/scala/vexriscv/demo/Murax.scala

@@ -12,6 +12,8 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
 import vexriscv.plugin._
 import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
 
+import scala.collection.mutable.ArrayBuffer
+
 /**
  * Created by PIC32F_USER on 28/07/2017.
  *
@@ -29,31 +31,105 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
 
 
 case class MuraxConfig(coreFrequency : HertzNumber,
-                       onChipRamSize : BigInt,
+                       onChipRamSize      : BigInt,
-                       onChipRamHexFile : String,
+                       onChipRamHexFile   : String,
-                       bypassExecute : Boolean,
+                       pipelineDBus       : Boolean,
-                       bypassMemory: Boolean,
+                       pipelineMainBus    : Boolean,
-                       bypassWriteBack: Boolean,
+                       pipelineApbBridge  : Boolean,
-                       bypassWriteBackBuffer : Boolean,
+                       gpioWidth          : Int,
-                       pipelineDBus : Boolean,
+                       uartCtrlConfig     : UartCtrlMemoryMappedConfig,
-                       pipelineMainBus : Boolean,
+                       cpuPlugins         : ArrayBuffer[Plugin[VexRiscv]]){
-                       pipelineApbBridge : Boolean){
   require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
 }
 
 object MuraxConfig{
   def default =  MuraxConfig(
-      coreFrequency         = 12 MHz,
+    coreFrequency         = 12 MHz,
-      onChipRamSize         = 8 kB,
+    onChipRamSize         = 8 kB,
-      onChipRamHexFile      = null,
+    onChipRamHexFile      = null,
-      bypassExecute         = false,
+    pipelineDBus          = true,
-      bypassMemory          = false,
+    pipelineMainBus       = false,
-      bypassWriteBack       = false,
+    pipelineApbBridge     = true,
-      bypassWriteBackBuffer = false,
+    gpioWidth = 32,
-      pipelineDBus          = true,
+    cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
-      pipelineMainBus       = false,
+      new PcManagerSimplePlugin(
-      pipelineApbBridge     = true
+        resetVector = 0x00000000l,
+        relaxedPcCalculation = true
+      ),
+      new IBusSimplePlugin(
+        interfaceKeepData = false,
+        catchAccessFault = false
+      ),
+      new DBusSimplePlugin(
+        catchAddressMisaligned = false,
+        catchAccessFault = false,
+        earlyInjection = false
+      ),
+      new CsrPlugin(CsrPluginConfig.smallest),
+      new DecoderSimplePlugin(
+        catchIllegalInstruction = false
+      ),
+      new RegFilePlugin(
+        regFileReadyKind = plugin.SYNC,
+        zeroBoot = true
+      ),
+      new IntAluPlugin,
+      new SrcPlugin(
+        separatedAddSub = false,
+        executeInsertion = false
+      ),
+      new LightShifterPlugin,
+      new HazardSimplePlugin(
+        bypassExecute = false,
+        bypassMemory = false,
+        bypassWriteBack = false,
+        bypassWriteBackBuffer = false,
+        pessimisticUseSrc = false,
+        pessimisticWriteRegFile = false,
+        pessimisticAddressMatch = false
+      ),
+      new BranchPlugin(
+        earlyBranch = false,
+        catchAddressMisaligned = false,
+        prediction = NONE
+      ),
+      new YamlPlugin("cpu0.yaml")
+    ),
+    uartCtrlConfig = UartCtrlMemoryMappedConfig(
+      uartCtrlConfig = UartCtrlGenerics(
+        dataWidthMax      = 8,
+        clockDividerWidth = 20,
+        preSamplingSize   = 1,
+        samplingSize      = 3,
+        postSamplingSize  = 1
+      ),
+      initConfig = UartCtrlInitConfig(
+        baudrate = 115200,
+        dataLength = 7,  //7 => 8 bits
+        parity = UartParityType.NONE,
+        stop = UartStopType.ONE
+      ),
+      busCanWriteClockDividerConfig = false,
+      busCanWriteFrameConfig = false,
+      txFifoDepth = 16,
+      rxFifoDepth = 16
+    )
+
   )
+
+  def fast = {
+    val config = default
+
+    //Replace HazardSimplePlugin to get datapath bypass
+    config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin(
+      bypassExecute = true,
+      bypassMemory = true,
+      bypassWriteBack = true,
+      bypassWriteBackBuffer = true
+    )
+
+    config
+  }
 }
 
 case class SimpleBusCmd() extends Bundle{
@@ -139,51 +215,7 @@ case class Murax(config : MuraxConfig) extends Component{
     //Instanciate the CPU
     val cpu = new VexRiscv(
       config = VexRiscvConfig(
-        plugins = List(
+        plugins = cpuPlugins += new DebugPlugin(debugClockDomain)
-          new PcManagerSimplePlugin(
-            resetVector = 0x00000000l,
-            relaxedPcCalculation = true
-          ),
-          new IBusSimplePlugin(
-            interfaceKeepData = false,
-            catchAccessFault = false
-          ),
-          new DBusSimplePlugin(
-            catchAddressMisaligned = false,
-            catchAccessFault = false,
-            earlyInjection = false
-          ),
-          new CsrPlugin(CsrPluginConfig.smallest),
-          new DecoderSimplePlugin(
-            catchIllegalInstruction = false
-          ),
-          new RegFilePlugin(
-            regFileReadyKind = plugin.SYNC,
-            zeroBoot = true
-          ),
-          new IntAluPlugin,
-          new SrcPlugin(
-            separatedAddSub = false,
-            executeInsertion = false
-          ),
-          new LightShifterPlugin,
-          new DebugPlugin(debugClockDomain),
-          new HazardSimplePlugin(
-            bypassExecute = bypassExecute,
-            bypassMemory = bypassMemory,
-            bypassWriteBack = bypassWriteBack,
-            bypassWriteBackBuffer = bypassWriteBackBuffer,
-            pessimisticUseSrc = false,
-            pessimisticWriteRegFile = false,
-            pessimisticAddressMatch = false
-          ),
-          new BranchPlugin(
-            earlyBranch = false,
-            catchAddressMisaligned = false,
-            prediction = NONE
-          ),
-          new YamlPlugin("cpu0.yaml")
-        )
       )
     )
 
@@ -379,30 +411,10 @@ case class Murax(config : MuraxConfig) extends Component{
     }
 
     val gpioACtrl = Apb3Gpio(
-      gpioWidth = 32
+      gpioWidth = gpioWidth
     )
     io.gpioA <> gpioACtrl.io.gpio
 
-    val uartCtrlConfig = UartCtrlMemoryMappedConfig(
-      uartCtrlConfig = UartCtrlGenerics(
-        dataWidthMax      = 8,
-        clockDividerWidth = 20,
-        preSamplingSize   = 1,
-        samplingSize      = 3,
-        postSamplingSize  = 1
-      ),
-      initConfig = UartCtrlInitConfig(
-        baudrate = 115200,
-        dataLength = 7,  //7 => 8 bits
-        parity = UartParityType.NONE,
-        stop = UartStopType.ONE
-      ),
-      busCanWriteClockDividerConfig = false,
-      busCanWriteFrameConfig = false,
-      txFifoDepth = 16,
-      rxFifoDepth = 16
-    )
-
     val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
     uartCtrl.io.uart <> io.uart
     externalInterrupt setWhen(uartCtrl.io.interrupt)
@@ -454,6 +466,7 @@ case class Murax(config : MuraxConfig) extends Component{
 object Murax{
   def main(args: Array[String]) {
     SpinalVerilog(Murax(MuraxConfig.default))
+//    SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) //dhrystone config (more ram)
   }
 }
 

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -107,12 +107,7 @@ object MuraxSynthesisBench {
       override def getName(): String = "MuraxFast"
       override def getRtlPath(): String = "MuraxFast.v"
       SpinalVerilog({
-        val murax = new Murax(MuraxConfig.default.copy(
+        val murax = new Murax(MuraxConfig.fast).setDefinitionName(getRtlPath().split("\\.").head)
-          bypassExecute         = true,
-          bypassMemory          = true,
-          bypassWriteBack       = true,
-          bypassWriteBackBuffer = true
-        )).setDefinitionName(getRtlPath().split("\\.").head)
         murax.io.mainClk.setName("clk")
         murax
       })