fpu add schedulerM2sPipe optino

src/main/scala/vexriscv/ip/fpu/FpuCore.scala

@@ -267,7 +267,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
 
   val cmdArbiter = new Area{
     val arbiter = StreamArbiterFactory.noLock.roundRobin.build(FpuCmd(p), portCount)
-    arbiter.io.inputs <> Vec(scheduler.map(_.output))
+    arbiter.io.inputs <> Vec(scheduler.map(_.output.pipelined(m2s = p.schedulerM2sPipe)))
 
     val output = arbiter.io.output.swapPayload(RfReadInput())
     output.source := arbiter.io.chosen

src/main/scala/vexriscv/ip/fpu/Interface.scala

@@ -119,6 +119,7 @@ case class FpuParameter( withDouble : Boolean,
                          asyncRegFile : Boolean = false,
                          mulWidthA : Int = 18,
                          mulWidthB : Int = 18,
+                         schedulerM2sPipe : Boolean = false,
                          sim : Boolean = false,
                          withAdd : Boolean = true,
                          withMul : Boolean = true,