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Update big endian instruction encoding 

Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
This commit is contained in:
Marcus Comstedt 2020-10-20 18:05:31 +02:00
parent 98de02051e
commit 6c8e97f825
1 changed files with 2 additions and 3 deletions
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5
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
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@ -373,10 +373,9 @@ class IBusSimplePlugin( resetVector : BigInt,
fetchRsp.rsp := rspBuffer.output.payload fetchRsp.rsp := rspBuffer.output.payload
fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin
if(bigEndian){ if(bigEndian){
// inst(15 downto 0) should contain lower addressed parcel, // instructions are stored in little endian byteorder
// and inst(31 downto 16) the higher addressed parcel
fetchRsp.rsp.inst.allowOverride fetchRsp.rsp.inst.allowOverride
fetchRsp.rsp.inst := rspBuffer.output.payload.inst.rotateLeft(16) fetchRsp.rsp.inst := EndiannessSwap(rspBuffer.output.payload.inst)
} }
val join = Stream(FetchRsp()) val join = Stream(FetchRsp())