Cfu add state index and cfu index
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@ -53,6 +53,7 @@ object GenSmallAndProductiveCfu extends App{
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new CfuPlugin(
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stageCount = 1,
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allowZeroLatency = true,
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cfuIndexWidth = 4,
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encodings = List(
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CfuPluginEncoding (
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instruction = M"-------------------------0001011",
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@ -63,13 +64,14 @@ object GenSmallAndProductiveCfu extends App{
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busParameter = CfuBusParameter(
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CFU_VERSION = 0,
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CFU_INTERFACE_ID_W = 0,
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CFU_FUNCTION_ID_W = 2,
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CFU_FUNCTION_ID_W = 7,
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CFU_REORDER_ID_W = 0,
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CFU_REQ_RESP_ID_W = 0,
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CFU_INPUTS = 2,
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CFU_INPUT_DATA_W = 32,
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CFU_OUTPUTS = 1,
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CFU_OUTPUT_DATA_W = 32,
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CFU_STATE_INDEX_NUM = 5,
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CFU_FLOW_REQ_READY_ALWAYS = false,
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CFU_FLOW_RESP_READY_ALWAYS = false
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)
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@ -25,6 +25,7 @@ case class CfuBusParameter(CFU_VERSION : Int = 0,
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CFU_FUNCTION_ID_W : Int,
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CFU_REORDER_ID_W : Int = 0,
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CFU_REQ_RESP_ID_W : Int = 0,
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CFU_STATE_INDEX_NUM : Int = 0,
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CFU_INPUTS : Int,
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CFU_INPUT_DATA_W : Int,
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CFU_OUTPUTS : Int,
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@ -37,7 +38,7 @@ case class CfuCmd( p : CfuBusParameter ) extends Bundle{
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val reorder_id = UInt(p.CFU_REORDER_ID_W bits)
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val request_id = UInt(p.CFU_REQ_RESP_ID_W bits)
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val inputs = Vec(Bits(p.CFU_INPUT_DATA_W bits), p.CFU_INPUTS)
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val state_index = UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits)
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def weakAssignFrom(m : CfuCmd): Unit ={
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def s = this
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WeakConnector(m, s, m.function_id, s.function_id, defaultValue = null, allowUpSize = false, allowDownSize = true , allowDrop = true)
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@ -87,12 +88,16 @@ object CfuPlugin{
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case class CfuPluginEncoding(instruction : MaskedLiteral,
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functionId : List[Range],
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input2Kind : CfuPlugin.Input2Kind.E)
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input2Kind : CfuPlugin.Input2Kind.E){
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val functionIdWidth = functionId.map(_.size).sum
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}
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class CfuPlugin( val stageCount : Int,
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val allowZeroLatency : Boolean,
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val busParameter : CfuBusParameter,
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val encodings : List[CfuPluginEncoding] = null) extends Plugin[VexRiscv]{
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class CfuPlugin(val stageCount : Int,
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val allowZeroLatency : Boolean,
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val busParameter : CfuBusParameter,
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val encodings : List[CfuPluginEncoding] = null,
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val stateAndIndexCsrOffset : Int = 0xBC0,
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val cfuIndexWidth : Int = 0) extends Plugin[VexRiscv]{
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def p = busParameter
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assert(p.CFU_INPUTS <= 2)
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@ -143,37 +148,25 @@ class CfuPlugin( val stageCount : Int,
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values = actions
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)
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}
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// decoderService.add(List(
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// //custom-0
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// M"-------------------------0001011" -> List(
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// CFU_ENABLE -> True,
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// REGFILE_WRITE_VALID -> True,
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// BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0),
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// BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1),
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// RS1_USE -> True,
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// RS2_USE -> True,
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// CFU_IMM -> False
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// ),
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//
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// //custom-1
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// M"-------------------------0101011" -> List(
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// CFU_ENABLE -> True,
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// REGFILE_WRITE_VALID -> True,
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// BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0),
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// BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1),
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// RS1_USE -> True,
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// CFU_IMM -> True
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// )
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// ))
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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val csr = pipeline plug new Area{
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val stateId = Reg(UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits)) init(0)
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if(p.CFU_STATE_INDEX_NUM > 1) {
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assert(stateAndIndexCsrOffset != -1, "CfuPlugin stateCsrIndex need to be set in the parameters")
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pipeline.service(classOf[CsrInterface]).rw(stateAndIndexCsrOffset, 16, stateId)
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}
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bus.cmd.state_index := stateId
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val cfuIndex = Reg(UInt(cfuIndexWidth bits)) init(0)
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if(cfuIndexWidth != 0){
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pipeline.service(classOf[CsrInterface]).rw(stateAndIndexCsrOffset, 0, cfuIndex)
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}
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}
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forkStage plug new Area{
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import forkStage._
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@ -186,8 +179,9 @@ class CfuPlugin( val stageCount : Int,
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arbitration.haltItself setWhen(bus.cmd.valid && !bus.cmd.ready)
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// bus.cmd.function_id := U(input(INSTRUCTION)(14 downto 12)).resized
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val functionsIds = encodings.map(e => U(Cat(e.functionId.map(r => input(INSTRUCTION)(r))), busParameter.CFU_FUNCTION_ID_W bits))
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bus.cmd.function_id := functionsIds.read(input(CFU_ENCODING))
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val functionIdFromInstructinoWidth = encodings.map(_.functionIdWidth).max
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val functionsIds = encodings.map(e => U(Cat(e.functionId.map(r => input(INSTRUCTION)(r))), functionIdFromInstructinoWidth bits))
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bus.cmd.function_id := csr.cfuIndex @@ functionsIds.read(input(CFU_ENCODING))
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bus.cmd.reorder_id := 0
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bus.cmd.request_id := 0
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if(p.CFU_INPUTS >= 1) bus.cmd.inputs(0) := input(RS1)
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