Cached wishbone demo is passing regression tests
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@ -15,8 +15,8 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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//
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//}
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//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON
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// make clean run DBUS=CACHED_WISHBONE IBUS=CACHED_WISHBONE MMU=no CSR=no DEBUG_PLUGIN=no
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object VexRiscvCachedWishboneForSim{
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def main(args: Array[String]) {
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val report = SpinalVerilog{
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@ -304,7 +304,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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def toWishbone(): Wishbone = {
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val wishboneConfig = p.getWishboneConfig()
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val bus = Wishbone(wishboneConfig)
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val counter = Reg(UInt(log2Up(p.burstSize) bits))
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val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
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val cmdBridge = Stream (DataCacheMemCmd(p))
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cmdBridge.valid := cmd.valid
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@ -333,11 +333,11 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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bus.WE := cmdBridge.wr
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bus.DAT_MOSI := cmdBridge.data
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cmdBridge.ready := bus.ACK
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cmdBridge.ready := cmdBridge.valid && bus.ACK
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bus.CYC := cmdBridge.valid
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bus.STB := cmdBridge.valid
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rsp.valid := RegNext(bus.WE && bus.ACK) init(False)
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rsp.valid := RegNext(cmdBridge.valid && !bus.WE && bus.ACK) init(False)
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rsp.data := RegNext(bus.DAT_MISO)
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rsp.error := False //TODO
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bus
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@ -168,7 +168,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
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def toWishbone(): Wishbone = {
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val wishboneConfig = p.getWishboneConfig()
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val bus = Wishbone(wishboneConfig)
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val counter = Reg(UInt(log2Up(p.burstSize) bits))
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val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
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val pending = counter =/= 0
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val lastCycle = counter === counter.maxValue
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@ -188,8 +188,8 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
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}
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}
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cmd.ready := !pending
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rsp.valid := RegNext(bus.ACK) init(False)
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cmd.ready := cmd.valid && bus.ACK
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rsp.valid := RegNext(bus.CYC && bus.ACK) init(False)
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rsp.data := RegNext(bus.DAT_MISO)
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rsp.error := False //TODO
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bus
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@ -686,6 +686,49 @@ public:
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};
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#endif
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#ifdef IBUS_CACHED_WISHBONE
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#include <queue>
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class IBusCachedWishbone : public SimElement{
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public:
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Workspace *ws;
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VVexRiscv* top;
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IBusCachedWishbone(Workspace* ws){
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this->ws = ws;
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this->top = ws->top;
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}
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virtual void onReset(){
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top->iBusWishbone_ACK = !ws->iStall;
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top->iBusWishbone_ERR = 0;
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}
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virtual void preCycle(){
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top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32);
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if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) {
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assertEq(top->iBusWishbone_ADR & 3,0);
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if(top->iBusWishbone_WE){
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} else {
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bool error;
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ws->iBusAccess(top->iBusWishbone_ADR,&top->iBusWishbone_DAT_MISO,&error);
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top->iBusWishbone_ERR = error;
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}
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}
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}
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virtual void postCycle(){
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if(ws->iStall)
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top->iBusWishbone_ACK = VL_RANDOM_I(7) < 100;
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}
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};
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#endif
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#ifdef DBUS_SIMPLE
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class DBusSimple : public SimElement{
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public:
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@ -782,8 +825,48 @@ public:
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};
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#endif
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#ifdef DBUS_CACHED_WISHBONE
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#include <queue>
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class DBusCachedWishbone : public SimElement{
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public:
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Workspace *ws;
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VVexRiscv* top;
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DBusCachedWishbone(Workspace* ws){
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this->ws = ws;
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this->top = ws->top;
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}
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virtual void onReset(){
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top->dBusWishbone_ACK = !ws->iStall;
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top->dBusWishbone_ERR = 0;
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}
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virtual void preCycle(){
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top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32);
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if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) {
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assertEq(top->dBusWishbone_ADR & 3,0);
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if(top->dBusWishbone_WE){
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bool dummy;
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ws->dBusAccess(top->dBusWishbone_ADR,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy);
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} else {
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bool error;
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ws->dBusAccess(top->dBusWishbone_ADR,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error);
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top->dBusWishbone_ERR = error;
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}
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}
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}
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virtual void postCycle(){
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if(ws->iStall)
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top->dBusWishbone_ACK = VL_RANDOM_I(7) < 100;
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}
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};
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#endif
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#ifdef DBUS_CACHED
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//#include "VVexRiscv_DataCache.h"
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@ -1216,6 +1299,9 @@ void Workspace::fillSimELements(){
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#ifdef IBUS_CACHED_AVALON
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simElements.push_back(new IBusCachedAvalon(this));
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#endif
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#ifdef IBUS_CACHED_WISHBONE
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simElements.push_back(new IBusCachedWishbone(this));
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#endif
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#ifdef DBUS_SIMPLE
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simElements.push_back(new DBusSimple(this));
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#endif
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@ -1228,6 +1314,9 @@ void Workspace::fillSimELements(){
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#ifdef DBUS_CACHED_AVALON
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simElements.push_back(new DBusCachedAvalon(this));
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#endif
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#ifdef DBUS_CACHED_WISHBONE
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simElements.push_back(new DBusCachedWishbone(this));
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#endif
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#ifdef DEBUG_PLUGIN_STD
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simElements.push_back(new DebugPluginStd(this));
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#endif
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