Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sim golden model lrsc reservation sync

This commit is contained in:
Dolu1990 2022-01-10 16:08:38 +01:00
parent da53de360f
commit 6e77f32087
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/test/cpp/regression/main.cpp
View File

@ -897,8 +897,8 @@ public:
dWrite(pAddr, size, (uint8_t*) &rsp.value);
status.fs = 3;
pcWrite(pc + 4);
lrscReserved = false;
}
lrscReserved = false;
} break;
#endif
case 0x37:rfWrite(rd32, i & 0xFFFFF000);pcWrite(pc + 4);break; // LUI
@ -949,8 +949,8 @@ public:
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
dWrite(pAddr, size, (uint8_t*)&i32_rs2);
pcWrite(pc + 4);
lrscReserved = false;
}
lrscReserved = false;
}break;
case 0x13: //ALUi
switch ((i >> 12) & 0x7) {